On Wed, Aug 9, 2017 at 2:37 AM, <stef...@marvell.com> wrote:
> From: Stefan Chulski <stef...@marvell.com>
> A8K marvell SoC has two South Bridge communication controllers(CP0 and CP1).
> Each communication controller has packet processor ports and MDIO.
> On MACHIATOBin board ports from CP1 are connected to mdio on CP0.
> Wrong base address is assigned to MDIO interface during probe.
> Get MDIO address from PHY handler parent base address.
> This should be refined in the future when MDIO driver is implemented.
> Signed-off-by: Stefan Chulski <stef...@marvell.com>
> Tested-by: iSoC Platform CI <ykj...@marvell.com>
> Reviewed-by: Igal Liberman <ig...@marvell.com>
Acked-by: Joe Hershberger <joe.hershber...@ni.com>
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