Rx Compliance tests may fail intermittently at high
jitter frequencies using default register values

Changes identified in test setup makes the Rx compliance test pass

Signed-off-by: Sriram Dash <sriram.d...@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bha...@nxp.com>
Signed-off-by: Suresh Gupta <suresh.bha...@nxp.com>
Signed-off-by: Ran Wang <ran.wan...@nxp.com>
---
Change in v2:
        In function erratum_a009007():
        1.Put a blank line after variable declaration.

 arch/arm/cpu/armv7/ls102xa/Kconfig                |  6 ++++++
 arch/arm/cpu/armv7/ls102xa/soc.c                  | 12 ++++++++++++
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h |  7 +++++++
 3 files changed, 25 insertions(+)

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig 
b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 0acff07..f45bb1d 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -8,6 +8,7 @@ config ARCH_LS1021A
        select SYS_FSL_ERRATUM_A009008
        select SYS_FSL_ERRATUM_A009798
        select SYS_FSL_ERRATUM_A008997
+       select SYS_FSL_ERRATUM_A009007
        select SYS_FSL_SRDS_1
        select SYS_HAS_SERDES
        select SYS_FSL_DDR_BE if SYS_FSL_DDR
@@ -69,6 +70,11 @@ config SYS_FSL_ERRATUM_A008997
        help
                Workaround for USB PHY erratum A008997
 
+config SYS_FSL_ERRATUM_A009007
+       bool
+       help
+               Workaround for USB PHY erratum A009007
+
 config SYS_FSL_SRDS_1
        bool
 
diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c
index 6f8eb0b..9e78344 100644
--- a/arch/arm/cpu/armv7/ls102xa/soc.c
+++ b/arch/arm/cpu/armv7/ls102xa/soc.c
@@ -93,6 +93,17 @@ static void erratum_a008997(void)
 #endif /* CONFIG_SYS_FSL_ERRATUM_A008997 */
 }
 
+static void erratum_a009007(void)
+{
+#ifdef CONFIG_SYS_FSL_ERRATUM_A009007
+       void __iomem *usb_phy = (void __iomem *)USB_PHY_BASE;
+
+       out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_1);
+       out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_2);
+       out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_3);
+       out_le16(usb_phy + USB_PHY_RX_OVRD_IN_HI, USB_PHY_RX_EQ_VAL_4);
+#endif /* CONFIG_SYS_FSL_ERRATUM_A009007 */
+}
 
 void s_init(void)
 {
@@ -184,6 +195,7 @@ int arch_soc_init(void)
        erratum_a009008();
        erratum_a009798();
        erratum_a008997();
+       erratum_a009007();
 
        return 0;
 }
diff --git a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h 
b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
index 539c1cf..703e59f 100644
--- a/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
+++ b/arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h
@@ -181,6 +181,13 @@ struct ccsr_gur {
 #define USB_PCSTXSWINGFULL_MASK        0x0000FE00
 #define USB_PCSTXSWINGFULL_VAL 0x00008E00
 
+#define USB_PHY_BASE                   0x08510000
+#define USB_PHY_RX_OVRD_IN_HI  0x200c
+#define USB_PHY_RX_EQ_VAL_1            0x0000
+#define USB_PHY_RX_EQ_VAL_2            0x8000
+#define USB_PHY_RX_EQ_VAL_3            0x8004
+#define USB_PHY_RX_EQ_VAL_4            0x800C
+
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
        u32 dpslpcr;
-- 
2.1.0.27.g96db324

_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot

Reply via email to