> -----Original Message-----
> From: Ashish Kumar [mailto:ashish.ku...@nxp.com]
> Sent: Friday, August 11, 2017 12:54 PM
> To: u-boot@lists.denx.de
> Cc: York Sun <york....@nxp.com>; Ashish Kumar <ashish.ku...@nxp.com>;
> Alison Wang <alison.w...@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushw...@nxp.com>; Raghav Dogra <raghav.do...@nxp.com>;
> Shaohui Xie <shaohui....@nxp.com>
> Subject: [PATCH v3 1/3] armv8: ls1088a: Add NXP LS1088A SoC support
> 
> The QorIQ LS1088A processor is built on the Layerscape
> architecture combining eight ARM A53 processor cores
> with advanced, high-performance datapath acceleration
> and networks, peripheral interfaces required for
> networking, wireless infrastructure, and general-purpose
> embedded applications.
> 
> LS1088A is compliant to the Layerscape Chassis Generation 3.
> 
> Features summary:
>  - Eight 32-bit / 64-bit ARM v8 Cortex-A53 CPUs
>  - Cores are in 2 cluster of 4-cores each
>  - Cache coherent interconnect (CCI-400)
>  - One 64-bit DDR4 SDRAM memory controller with ECC
>  - Data path acceleration architecture 2.0 (DPAA2)
>  - Ethernet interfaces: SGMIIs, RGMIIs, QSGMIIs, XFIs
>  - QSPI, IFC, 3 PCIe, 1 SATA, 2 USB, 1 SDXC, 2 DUARTs etc
> 
> Signed-off-by: Alison Wang <alison.w...@nxp.com>
> Signed-off-by: Prabhakar Kushwaha <prabhakar.kushw...@nxp.com>
> Signed-off-by: Ashish Kumar <ashish.ku...@nxp.com>
> Signed-off-by: Raghav Dogra <raghav.do...@nxp.com>
> Signed-off-by: Shaohui Xie <shaohui....@nxp.com>
> ---
> 
> v2:
>  Fix indentaion in commit msg
>  Separate RDB and Si specific file
>  Move Macros to Kconfig
> 
> v3:
> 1.Re-based on top of
>   commit d529124fdcf941c34074fd1ce600f4b1b4a7dd07
>   Merge: f0ca30f 6a5691e
>   Author: Tom Rini <tr...@konsulko.com>
>   Date:   Tue Aug 8 17:06:19 2017 -0400
> 
>     Merge git://git.denx.de/u-boot-x86
> 
> 2.Incorporate review comments on v2
>   Clean up done
> 
> 3.Migrate changes from ls1088ardb_stream_id.h to stream_id_lsch3.h
> 
>  arch/arm/cpu/armv8/fsl-layerscape/Kconfig          |  39 ++++++-
>  arch/arm/cpu/armv8/fsl-layerscape/Makefile         |   4 +
>  .../cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c    |  10 ++
>  arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S       |   6 +-
>  arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 126
> +++++++++++++++++++++
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c            |   5 +
>  arch/arm/dts/fsl-ls1088a.dtsi                      |  78 +++++++++++++
>  arch/arm/include/asm/arch-fsl-layerscape/config.h  |  62 +++++++++-
>  arch/arm/include/asm/arch-fsl-layerscape/cpu.h     |   4 +
>  .../include/asm/arch-fsl-layerscape/fsl_serdes.h   |   3 +-
>  .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  11 ++
>  arch/arm/include/asm/arch-fsl-layerscape/soc.h     |   4 +
>  .../asm/arch-fsl-layerscape/stream_id_lsch3.h      |  14 +++
>  drivers/ddr/fsl/util.c                             |   2 +-
>  drivers/net/ldpaa_eth/Makefile                     |   1 +
>  drivers/net/ldpaa_eth/ls1088a.c                    |  87 ++++++++++++++


Add SoC details in arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc

>  16 files changed, 447 insertions(+), 9 deletions(-)
>  create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
>  create mode 100644 arch/arm/dts/fsl-ls1088a.dtsi
>  create mode 100644 drivers/net/ldpaa_eth/ls1088a.c
> 

> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> index 1132969..a3c7490 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
> @@ -49,6 +49,29 @@ config ARCH_LS1046A
>       select BOARD_EARLY_INIT_F
>       imply SCSI
> 
> +config ARCH_LS1088A
> +     bool
> +     select ARMV8_SET_SMPEN
> +     select FSL_LSCH3
> +     select SYS_FSL_DDR
> +     select SYS_FSL_DDR_LE
> +     select SYS_FSL_DDR_VER_50
> +     select SYS_FSL_ERRATUM_A009803
> +     select SYS_FSL_ERRATUM_A009942
> +     select SYS_FSL_ERRATUM_A010165
> +     select SYS_FSL_ERRATUM_A008511
> +     select SYS_FSL_ERRATUM_A008850
> +     select SYS_FSL_HAS_CCI400
> +     select SYS_FSL_HAS_DDR4
> +     select SYS_FSL_HAS_SEC
> +     select SYS_FSL_SEC_COMPAT_5
> +     select SYS_FSL_SEC_LE
> +     select SYS_FSL_SRDS_1
> +     select SYS_FSL_SRDS_2
> +     select FSL_TZASC_1
> +     select ARCH_EARLY_INIT_R
> +     select BOARD_EARLY_INIT_F
> +
>  config ARCH_LS2080A
>       bool
>       select ARMV8_SET_SMPEN
> @@ -60,6 +83,7 @@ config ARCH_LS2080A
>       select SYS_FSL_DDR
>       select SYS_FSL_DDR_LE
>       select SYS_FSL_DDR_VER_50
> +     select SYS_FSL_HAS_CCN504
>       select SYS_FSL_HAS_DP_DDR
>       select SYS_FSL_HAS_SEC
>       select SYS_FSL_HAS_DDR4
> @@ -98,7 +122,7 @@ config FSL_LSCH3
> 
>  config FSL_MC_ENET
>       bool "Management Complex network"
> -     depends on ARCH_LS2080A
> +     depends on ARCH_LS2080A || ARCH_LS1088A
>       default y
>       select RESV_RAM
>       help
> @@ -114,6 +138,7 @@ config FSL_PCIE_COMPAT
>       default "fsl,ls1043a-pcie" if ARCH_LS1043A
>       default "fsl,ls1046a-pcie" if ARCH_LS1046A
>       default "fsl,ls2080a-pcie" if ARCH_LS2080A
> +     default "fsl,ls1080a-pcie" if ARCH_LS1088A
>       help
>         This compatible is used to find pci controller node in Kernel DT
>         to complete fixup.
> @@ -228,6 +253,7 @@ config MAX_CPUS
>       default 4 if ARCH_LS1043A
>       default 4 if ARCH_LS1046A
>       default 16 if ARCH_LS2080A
> +     default 8 if ARCH_LS1088A
>       default 1
>       help
>         Set this number to the maximum number of possible CPUs in the SoC.
> @@ -259,14 +285,17 @@ config SYS_CCI400_OFFSET
> 
>  config SYS_FSL_IFC_BANK_COUNT
>       int "Maximum banks of Integrated flash controller"
> -     depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
> +     depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A ||
> ARCH_LS1088A
>       default 4 if ARCH_LS1043A
>       default 4 if ARCH_LS1046A
> -     default 8 if ARCH_LS2080A
> +     default 8 if ARCH_LS2080A || ARCH_LS1088A
> 
>  config SYS_FSL_HAS_CCI400
>       bool
> 
> +config SYS_FSL_HAS_CCN504
> +     bool
> +
>  config SYS_FSL_HAS_DP_DDR
>       bool
> 
> @@ -308,6 +337,7 @@ config SYS_FSL_PCLK_DIV
>       int "Platform clock divider"
>       default 1 if ARCH_LS1043A
>       default 1 if ARCH_LS1046A
> +     default 1 if ARCH_LS1088A
>       default 2
>       help
>         This is the divider that is used to derive Platform clock from
> @@ -401,7 +431,8 @@ config SYS_FSL_ERRATUM_A009929
>  config SYS_MC_RSV_MEM_ALIGN
>       hex "Management Complex reserved memory alignment"
>       depends on RESV_RAM
> -     default 0x20000000
> +     default 0x20000000 if ARCH_LS2080A
> +     default 0x70000000 if ARCH_LS1088A
>       help
>         Reserved memory needs to be aligned for MC to use. Default value
>         is 512MB.
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> index e3ce018..115c3fc 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> @@ -38,3 +38,7 @@ endif
>  ifneq ($(CONFIG_ARCH_LS1046A),)
>  obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
>  endif
> +
> +ifneq ($(CONFIG_ARCH_LS1088A),)
> +obj-$(CONFIG_SYS_HAS_SERDES) += ls1088a_serdes.o
> +endif
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> index ef97556..13def18 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
> @@ -28,6 +28,11 @@ __weak void wriop_init_dpmac_qsgmii(int sd, int
> lane_prtcl)
>       return;
>  }
> 
> +__weak int serdes_get_number(int serdes, int cfg)
> +{
> +     return cfg;
> +}
> +
>  int is_serdes_configured(enum srds_prtcl device)
>  {
>       int ret = 0;
> @@ -73,6 +78,9 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
>               printf("invalid SerDes%d\n", sd);
>               break;
>       }
> +
> +     cfg = serdes_get_number(sd, cfg);
> +
>       /* Is serdes enabled at all? */
>       if (cfg == 0)
>               return -ENODEV;
> @@ -99,6 +107,8 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32
> sd_prctl_mask,
> 
>       cfg = gur_in32(&gur->rcwsr[rcwsr - 1]) & sd_prctl_mask;
>       cfg >>= sd_prctl_shift;
> +
> +     cfg = serdes_get_number(sd, cfg);
>       printf("Using SERDES%d Protocol: %d (0x%x)\n", sd + 1, cfg, cfg);
> 
>       if (!is_serdes_prtcl_valid(sd, cfg))
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> index 3136e3f..d943f84 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
> @@ -76,7 +76,7 @@ ENTRY(lowlevel_init)
>       switch_el x1, 1f, 100f, 100f    /* skip if not in EL3 */
>  1:
> 
> -#ifdef CONFIG_FSL_LSCH3
> +#if defined(CONFIG_FSL_LSCH3) && defined (CONFIG_SYS_FSL_HAS_CCN504)
> 

Is it possible to put patch having CONFIG_SYS_FSL_HAS_CCN504 defined and then 
SoC patch

>       /* Set Wuo bit for RN-I 20 */
>  #ifdef CONFIG_ARCH_LS2080A
> @@ -338,7 +338,9 @@ get_svr:
>       ldr     x1, =FSL_LSCH3_SVR
>       ldr     w0, [x1]
>       ret
> +#endif
> 
> +#ifdef CONFIG_SYS_FSL_HAS_CCN504
>  hnf_pstate_poll:
>       /* x0 has the desired status, return 0 for success, 1 for timeout
>        * clobber x1, x2, x3, x4, x6, x7
> @@ -420,7 +422,7 @@ ENTRY(__asm_flush_l3_dcache)
>       mov     lr, x29
>       ret
>  ENDPROC(__asm_flush_l3_dcache)
> -#endif
> +#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
> 
>  #ifdef CONFIG_MP
>       /* Keep literals not used by the secondary boot code outside it */
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
> new file mode 100644
> index 0000000..9f5cdd5
> --- /dev/null
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c
> @@ -0,0 +1,126 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +#include <common.h>
> +#include <asm/arch/fsl_serdes.h>
> +
> +struct serdes_config {
> +     u8 ip_protocol;
> +     u8 lanes[SRDS_MAX_LANES];
> +     u8 rcw_lanes[SRDS_MAX_LANES];
> +};
> +
> +static struct serdes_config serdes1_cfg_tbl[] = {
> +     /* SerDes 1 */
> +     {0x12, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 3 }  },
> +     {0x15, {SGMII3, SGMII7, XFI1, XFI2 }, {3, 3, 1, 1 } },
> +     {0x16, {SGMII3, SGMII7, SGMII1, XFI2 }, {3, 3, 3, 1 } },
> +     {0x17, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 3, 2 } },
> +     {0x18, {SGMII3, SGMII7, SGMII1, SGMII2 }, {3, 3, 2, 2 } },
> +     {0x19, {SGMII3, QSGMII_B, XFI1, XFI2}, {3, 4, 1, 1 } },
> +     {0x1A, {SGMII3, QSGMII_B, SGMII1, XFI2 }, {3, 4, 3, 1 } },
> +     {0x1B, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 2 } },
> +     {0x1C, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 2, 2 } },
> +     {0x1D, {QSGMII_A, QSGMII_B, XFI1, XFI2 }, {4, 4, 1, 1 } },
> +     {0x1E, {QSGMII_A, QSGMII_B, SGMII1, XFI2  }, {4, 4, 3, 1 } },
> +     {0x1F, {QSGMII_A, QSGMII_B, SGMII1, SGMII2  }, {4, 4, 3, 2 } },
> +     {0x20, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 2, 2 } },
> +     {0x35, {SGMII3, QSGMII_B, SGMII1, SGMII2 }, {3, 4, 3, 3 } },
> +     {0x36, {QSGMII_A, QSGMII_B, SGMII1, SGMII2 }, {4, 4, 3, 3 } },
> +     {0x3A, {SGMII3, PCIE1, SGMII1, SGMII2 }, {3, 5, 3, 3 } },
> +             {}
> +};
> +static struct serdes_config serdes2_cfg_tbl[] = {
> +     /* SerDes 2 */
> +     {0x0C, {PCIE1, PCIE1, PCIE1, PCIE1 }, {8, 8, 8, 8 } },
> +     {0x0D, {PCIE1, PCIE2, PCIE3, SATA1 }, {5, 5, 5, 9 }  },
> +     {0x0E, {PCIE1, PCIE1, PCIE2, SATA1 }, {7, 7, 6, 9 }  },
> +     {0x13, {PCIE1, PCIE1, PCIE3, PCIE3 }, {7, 7, 7, 7 }  },
> +     {0x14, {PCIE1, PCIE2, PCIE3, PCIE3 }, {5, 5, 7, 7 }  },
> +     {0x3C, {NONE, PCIE2, NONE, PCIE3 }, {0, 5, 0, 6 }  },
> +     {}
> +};
> +
> +static struct serdes_config *serdes_cfg_tbl[] = {
> +     serdes1_cfg_tbl,
> +     serdes2_cfg_tbl,
> +};
> +
> +int serdes_get_number(int serdes, int cfg)
> +{
> +     struct serdes_config *ptr;
> +     int i, j, index, lnk;
> +     int is_found, max_lane = SRDS_MAX_LANES;
> +
> +     if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
> +             return 0;
> +
> +     ptr = serdes_cfg_tbl[serdes];
> +
> +     while (ptr->ip_protocol) {
> +             is_found = 1;
> +             for (i = 0, j = max_lane - 1; i < max_lane; i++, j--) {
> +                     lnk = cfg & (0xf << 4 * i);
> +                     lnk = lnk >> (4 * i);
> +
> +                     index = (serdes == FSL_SRDS_1) ? j : i;
> +
> +                     if (ptr->rcw_lanes[index] == lnk && is_found)
> +                             is_found = 1;
> +                     else
> +                             is_found = 0;
> +             }
> +
> +             if (is_found)
> +                     return ptr->ip_protocol;
> +             ptr++;
> +     }
> +
> +     return 0;
> +}
> +
> +enum srds_prtcl serdes_get_prtcl(int serdes, int cfg, int lane)
> +{
> +     struct serdes_config *ptr;
> +
> +     if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
> +             return 0;
> +
> +     ptr = serdes_cfg_tbl[serdes];
> +     while (ptr->ip_protocol) {
> +             if (ptr->ip_protocol == cfg)
> +                     return ptr->lanes[lane];
> +             ptr++;
> +     }
> +
> +     return 0;
> +}
> +
> +int is_serdes_prtcl_valid(int serdes, u32 prtcl)
> +{
> +     int i;
> +     struct serdes_config *ptr;
> +
> +     if (serdes >= ARRAY_SIZE(serdes_cfg_tbl))
> +             return 0;
> +
> +     ptr = serdes_cfg_tbl[serdes];
> +     while (ptr->ip_protocol) {
> +             if (ptr->ip_protocol == prtcl)
> +                     break;
> +             ptr++;
> +     }
> +
> +     if (!ptr->ip_protocol)
> +             return 0;
> +
> +     for (i = 0; i < SRDS_MAX_LANES; i++) {
> +             if (ptr->lanes[i] != NONE)
> +                     return 1;
> +     }
> +
> +     return 0;
> +}
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index ddb7d82..18820f6 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -24,6 +24,7 @@
>  #ifdef CONFIG_CHAIN_OF_TRUST
>  #include <fsl_validate.h>
>  #endif
> +#include <fsl_immap.h>
> 
>  DECLARE_GLOBAL_DATA_PTR;
> 
> @@ -215,11 +216,14 @@ int sata_init(void)
>  {
>       struct ccsr_ahci __iomem *ccsr_ahci;
> 
> +#ifdef CONFIG_SYS_SATA2
>       ccsr_ahci  = (void *)CONFIG_SYS_SATA2;
>       out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
>       out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
>       out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG);
> +#endif
> 
> +#ifdef CONFIG_SYS_SATA1
>       ccsr_ahci  = (void *)CONFIG_SYS_SATA1;
>       out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG);
>       out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG);
> @@ -227,6 +231,7 @@ int sata_init(void)
> 
>       ahci_init((void __iomem *)CONFIG_SYS_SATA1);
>       scsi_scan(false);
> +#endif
> 

CONFIG_SYS_SATA2, CONFIG_SYS_SATA1 should be separate patch. It should not part 
of SoC patch set.

>       return 0;
>  }
> diff --git a/arch/arm/dts/fsl-ls1088a.dtsi b/arch/arm/dts/fsl-ls1088a.dtsi
> new file mode 100644
> index 0000000..421d2de
> --- /dev/null
> +++ b/arch/arm/dts/fsl-ls1088a.dtsi
> @@ -0,0 +1,78 @@
> +/*
> + * NXP ls1088a SOC common device tree source
> + *
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier:  GPL-2.0+
> + */
> +
> +/ {
> +     compatible = "fsl,ls1088a";
> +     interrupt-parent = <&gic>;
> +     #address-cells = <2>;
> +     #size-cells = <2>;
> +
> +     memory@80000000 {
> +             device_type = "memory";
> +             reg = <0x00000000 0x80000000 0 0x80000000>;
> +                   /* DRAM space - 1, size : 2 GB DRAM */
> +     };
> +
> +     gic: interrupt-controller@6000000 {
> +             compatible = "arm,gic-v3";
> +             reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */
> +                   <0x0 0x06100000 0 0x100000>; /* GICR (RD_base +
> SGI_base) */
> +             #interrupt-cells = <3>;
> +             interrupt-controller;
> +             interrupts = <1 9 0x4>;
> +     };
> +
> +     timer {
> +             compatible = "arm,armv8-timer";
> +             interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
> +                          <1 14 0x8>, /* Physical Non-Secure PPI, active-low
> */
> +                          <1 11 0x8>, /* Virtual PPI, active-low */
> +                          <1 10 0x8>; /* Hypervisor PPI, active-low */
> +     };
> +
> +     serial0: serial@21c0500 {
> +             device_type = "serial";
> +             compatible = "fsl,ns16550", "ns16550a";
> +             reg = <0x0 0x21c0500 0x0 0x100>;
> +             clock-frequency = <0>;  /* Updated by bootloader */
> +             interrupts = <0 32 0x1>; /* edge triggered */
> +     };
> +
> +     serial1: serial@21c0600 {
> +             device_type = "serial";
> +             compatible = "fsl,ns16550", "ns16550a";
> +             reg = <0x0 0x21c0600 0x0 0x100>;
> +             clock-frequency = <0>;  /* Updated by bootloader */
> +             interrupts = <0 32 0x1>; /* edge triggered */
> +     };
> +
> +     fsl_mc: fsl-mc@80c000000 {
> +             compatible = "fsl,qoriq-mc";
> +             reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
> +                   <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
> +     };
> +
> +     dspi: dspi@2100000 {
> +             compatible = "fsl,vf610-dspi";
> +             #address-cells = <1>;
> +             #size-cells = <0>;
> +             reg = <0x0 0x2100000 0x0 0x10000>;
> +             interrupts = <0 26 0x4>; /* Level high type */
> +             num-cs = <6>;
> +     };
> +
> +     qspi: quadspi@1550000 {
> +             compatible = "fsl,vf610-qspi";
> +             #address-cells = <1>;
> +             #size-cells = <0>;
> +             reg = <0x0 0x20c0000 0x0 0x10000>,
> +                     <0x0 0x20000000 0x0 0x10000000>;
> +             reg-names = "QuadSPI", "QuadSPI-memory";
> +             num-cs = <4>;
> +     };
> +};
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> index 79e94f9..a7098be 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
> @@ -116,6 +116,67 @@
>  #define CONFIG_SYS_FSL_ERRATUM_A008751
> 
>  #define CONFIG_SYS_FSL_MAX_NUM_OF_SEC                1
> +
> +#elif defined(CONFIG_ARCH_LS1088A)
> +#define CONFIG_SYS_FSL_NUM_CC_PLLS           3
> +#define CONFIG_SYS_FSL_CLUSTER_CLOCKS                { 1, 1 }
> +#define CONFIG_GICV3
> +#define CONFIG_FSL_TZPC_BP147
> +#define CONFIG_FSL_TZASC_400
> +#define CONFIG_SYS_PAGE_SIZE         0x10000
> +
> +#define      SRDS_MAX_LANES  4
> +
> +/* TZ Protection Controller Definitions */
> +#define TZPC_BASE                            0x02200000
> +#define TZPCR0SIZE_BASE                              (TZPC_BASE)
> +#define TZPCDECPROT_0_STAT_BASE                      (TZPC_BASE + 0x800)
> +#define TZPCDECPROT_0_SET_BASE                       (TZPC_BASE + 0x804)
> +#define TZPCDECPROT_0_CLR_BASE                       (TZPC_BASE + 0x808)
> +#define TZPCDECPROT_1_STAT_BASE                      (TZPC_BASE + 0x80C)
> +#define TZPCDECPROT_1_SET_BASE                       (TZPC_BASE + 0x810)
> +#define TZPCDECPROT_1_CLR_BASE                       (TZPC_BASE + 0x814)
> +#define TZPCDECPROT_2_STAT_BASE                      (TZPC_BASE + 0x818)
> +#define TZPCDECPROT_2_SET_BASE                       (TZPC_BASE + 0x81C)
> +#define TZPCDECPROT_2_CLR_BASE                       (TZPC_BASE + 0x820)
> +
> +/* Generic Interrupt Controller Definitions */
> +#define GICD_BASE                    0x06000000
> +#define GICR_BASE                    0x06100000
> +
> +/* SMMU Defintions */
> +#define SMMU_BASE                    0x05000000 /* GR0 Base */
> +
> +/* DDR */
> +#define CONFIG_SYS_DDR_BLOCK1_SIZE   ((phys_size_t)2 << 30)
> +#define CONFIG_MAX_MEM_MAPPED
>       CONFIG_SYS_DDR_BLOCK1_SIZE
> +
> +#define CONFIG_SYS_FSL_CCSR_GUR_LE
> +#define CONFIG_SYS_FSL_CCSR_SCFG_LE
> +#define CONFIG_SYS_FSL_ESDHC_LE
> +#define CONFIG_SYS_FSL_IFC_LE
> +#define CONFIG_SYS_FSL_PEX_LUT_LE
> +
> +#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
> +
> +/* SFP */
> +#define CONFIG_SYS_FSL_SFP_VER_3_4
> +#define CONFIG_SYS_FSL_SFP_LE
> +#define CONFIG_SYS_FSL_SRK_LE
> +
> +/* Security Monitor */
> +#define CONFIG_SYS_FSL_SEC_MON_LE
> +
> +/* Secure Boot */
> +#define CONFIG_ESBC_HDR_LS
> +
> +/* DCFG - GUR */
> +#define CONFIG_SYS_FSL_CCSR_GUR_LE
> +#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC        1
> +#define CONFIG_SYS_FSL_OCRAM_BASE    0x18000000 /* initial RAM */
> +#define SYS_FSL_OCRAM_SPACE_SIZE     0x00200000 /* 2M space */
> +#define CONFIG_SYS_FSL_OCRAM_SIZE    0x00020000 /* Real size 128K */
> +


Are these offset different than LS2080A, if not move these definition to common 
place to avoid repetition. . 

--prabhakar
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