On 12/08/2017 16:10, Peng Fan wrote:
> This EPDC/EPXP QoS setting is needed for EPDC stress test to pass.
>
> Signed-off-by: Peng Fan <peng....@nxp.com>
> Cc: Stefano Babic <sba...@denx.de>
> Cc: Fabio Estevam <fabio.este...@nxp.com>
> ---
> arch/arm/include/asm/arch-mx7/imx-regs.h | 5 +++++
> arch/arm/mach-imx/mx7/soc.c | 38
> ++++++++++++++++++++++++++++++++
> 2 files changed, 43 insertions(+)
>
> diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h
> b/arch/arm/include/asm/arch-mx7/imx-regs.h
> index aab3a9a..a6b2091 100644
> --- a/arch/arm/include/asm/arch-mx7/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h
> @@ -152,6 +152,11 @@
> #define IP2APB_AXIMON_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1E0000)
> #define QOSC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR+0x1F0000)
>
> +#define REGS_QOS_BASE QOSC_IPS_BASE_ADDR
> +#define REGS_QOS_EPDC (QOSC_IPS_BASE_ADDR + 0x3400)
> +#define REGS_QOS_PXP0 (QOSC_IPS_BASE_ADDR + 0x2C00)
> +#define REGS_QOS_PXP1 (QOSC_IPS_BASE_ADDR + 0x3C00)
> +
> /* AIPS_TZ#3 - Global enable (0) */
> #define ECSPI1_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x20000)
> #define ECSPI2_BASE_ADDR (AIPS_TZ3_BASE_ADDR+0x30000)
> diff --git a/arch/arm/mach-imx/mx7/soc.c b/arch/arm/mach-imx/mx7/soc.c
> index 4307ae0..6b37848 100644
> --- a/arch/arm/mach-imx/mx7/soc.c
> +++ b/arch/arm/mach-imx/mx7/soc.c
> @@ -230,6 +230,42 @@ static void imx_enet_mdio_fixup(void)
> }
> }
>
> +static void set_epdc_qos(void)
> +{
> + /* Disable clkgate & soft_reset */
> + writel(0, REGS_QOS_BASE);
> + /* Enable all masters */
> + writel(0, REGS_QOS_BASE + 0x60);
> + /* Disable clkgate & soft_reset */
> + writel(0, REGS_QOS_EPDC);
> + /* Disable clkgate & soft_reset */
> + writel(0, REGS_QOS_PXP0);
> + /* Disable clkgate & soft_reset */
> + writel(0, REGS_QOS_PXP1);
> + /* WR, init = 7 with red flag */
> + writel(0x0f020722, REGS_QOS_EPDC + 0xd0);
> + /* RD, init = 7 with red flag */
> + writel(0x0f020722, REGS_QOS_EPDC + 0xe0);
> + /* OT_CTRL_EN =1 */
> + writel(1, REGS_QOS_PXP0);
> + /* OT_CTRL_EN =1 */
> + writel(1, REGS_QOS_PXP1);
> + /* WR, init = 2 with red flag */
> + writel(0x0f020222, REGS_QOS_PXP0 + 0x50);
> + /* WR, init = 2 with red flag */
> + writel(0x0f020222, REGS_QOS_PXP1 + 0x50);
> + /* rD, init = 2 with red flag */
> + writel(0x0f020222, REGS_QOS_PXP0 + 0x60);
> + /* rD, init = 2 with red flag */
> + writel(0x0f020222, REGS_QOS_PXP1 + 0x60);
> + /* tOTAL, init = 4 with red flag */
> + writel(0x0f020422, REGS_QOS_PXP0 + 0x70);
> + /* TOTAL, init = 4 with red flag */
> + writel(0x0f020422, REGS_QOS_PXP1 + 0x70);
> + /* EPDC AW/AR CACHE ENABLE */
> + writel(0xe080, IOMUXC_GPR_BASE_ADDR + 0x0034);
> +}
Comments are xhaustive, but can you set appropriate #define for all
constants ?
Best regards,
Stefano Babic
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