From: Tien Fong Chee <[email protected]> This patch adding the Intel Arria 10 SoCFPGA chosen binding info.
Signed-off-by: Tien Fong Chee <[email protected]> --- doc/device-tree-bindings/chosen.txt | 45 +++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-) diff --git a/doc/device-tree-bindings/chosen.txt b/doc/device-tree-bindings/chosen.txt index 5625d21..09473a5 100644 --- a/doc/device-tree-bindings/chosen.txt +++ b/doc/device-tree-bindings/chosen.txt @@ -63,3 +63,48 @@ Example u-boot,spl-boot-order = &sdmmc, "/sdhci@fe330000"; }; }; + +Intel SoCFPGA +-------------- + +Arria 10 FPGA design filename and partition properties +------------------------------------------------------ +In Intel Arria 10 SoCFPGA, FPGA is programmed by both SPL and U-boot. +Those FPGA designs are normally stored in the flashes, it could be in SDMMC, +QSPI and NAND. +For bootloader to know where to look those files and how to program the FPGA, +those files' filename, and flash partition are defined in device tree. +There are three properties as shown in below: + +Example +------- +/ { + chosen { + cff-file = "ghrd_10as066n2.periph.rbf.mkimage"; + }; +}; + +cff-file is assigned with peripheral raw binary filename. Peripheral raw binary +file is used to configure FPGA IOs, IO48, DDR and PLL. + +/ { + chosen { + cffcore-file = "ghrd_10as066n2.core.rbf.mkimage"; + }; +}; + +cffcore-file is assigned with core raw binary filename. Core raw binary +file contains FPGA design, which is used to configure FPGA CRAM and ERAM. + +/ { + chosen { + cff_devpart = "0:1"; + }; +}; + +cff_devpart is assigned to partition(default: FAT) where cff-file and +cffcore-file are stored. +[<dev{:part}>] dev is flash device number and part is flash partition. + +Note: For cff-file, the device number is always zero, and only the partition +could be defined by user. -- 1.7.7.4 _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
