> The clk_saradc is dividing from the 24M, clk_saradc=24MHz/(saradc_div_con+1). > Saradc integer divider control register is 8-bits width. > > Signed-off-by: David Wu <[email protected]> > --- > drivers/clk/rockchip/clk_rk3399.c | 34 ++++++++++++++++++++++++++++++++++ > 1 file changed, 34 insertions(+) >
Acked-by: Philipp Tomsich <[email protected]> _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
