Hi Vikas On 09/26/2017 10:51 AM, Patrice CHOTARD wrote: > Hi Vikas > > On 09/25/2017 09:51 AM, Patrice CHOTARD wrote: >> Hi Vikas >> >> On 09/20/2017 03:39 AM, Vikas Manocha wrote: >>> Hi Patrice, >>> >>> On 09/13/2017 09:00 AM, patrice.chot...@st.com wrote: >>>> From: Patrice Chotard <patrice.chot...@st.com> >>>> >>>> This driver implements basic clock setup, only clock gating >>>> is implemented. >>>> >>>> This driver doesn't implement .of_match as it's binded >>>> by MFD RCC driver. >>>> >>>> Files include/dt-bindings/clock/stm32h7-clks.h and >>>> doc/device-tree-bindings/clock/st,stm32h7-rcc.txt >>>> will be available soon in a kernel tag, as all the >>>> bindings have been acked by Rob Herring [1]. >>>> >>>> [1] http://lkml.iu.edu/hypermail/linux/kernel/1704.0/00935.html >>>> >>>> Signed-off-by: Patrice Chotard <patrice.chot...@st.com> >>>> --- > > [...] > >>>> + >>>> +#define PWR_CR3 0x0c >>>> +#define PWR_CR3_SDEN BIT(2) >>> >>> Can we use SCUEN suffix to match the Ref Manual. >> >> Which version of reference manual do you use ? in mine its SDEN, but i >> propably use a too old ref manual. >> > > I have found the last version of STM32H7 ref manual, mine was too old, > ok i will update the PWR_CR3_SDEN to PWR_CR3_SCUEN
After double check, in the STM32H7x3 reference manual available on st.com (DocID029587 Rev 2), bit 2 of PWR_CR3 reg is described as following: "Bit 2 SCUEN: Supply configuration update enable This bit is read-only: 0: Supply configuration update locked. 1: Single write enabled to Supply configuration (LDOEN and BYPASS)" Whereas in the one i used, bit 2 of PWR_CR3 is described as: "Bit 2 SDEN (1)(2) : SD converter Enable 0: Step down converter disabled 1: Step down converter enabled. (Default)" If i follow ref manual DocID029587 Rev 2, this bit is read-only, so the write access of PWR_CR3 bit(2) in clk_stm32h7.c is useless. But after write access removal, the both STM32H7 disco and eval board doesn't boot. The reference manual is wrong regarding with at least this bit. I will contact PWR architect to solve this point. Patrice > > thanks > > Patrice > >>> >>>> +#define PWR_D3CR 0x18 >>>> +#define PWR_D3CR_VOS_MASK GENMASK(15, 14) >>>> +#define PWR_D3CR_VOS_SHIFT 14 >>>> +#define VOS_SCALE_3 1 >>>> +#define VOS_SCALE_2 2 >>>> +#define VOS_SCALE_1 3 >>>> +#define PWR_D3CR_VOSREADY BIT(13) _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot