From: Jagan Teki <ja...@amarulasolutions.com>
configure_l2ctlr will be shared between SPL and TPL so
move them into asm/arch/sys_proto.h
Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
Changes for v2:
- New patch
arch/arm/include/asm/arch-rockchip/sys_proto.h | 23 +++++++++++++++++++++++
arch/arm/mach-rockchip/rk3288-board-spl.c | 21 +--------------------
2 files changed, 24 insertions(+), 20 deletions(-)
diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h
b/arch/arm/include/asm/arch-rockchip/sys_proto.h
index 35423e1..e428d59 100644
--- a/arch/arm/include/asm/arch-rockchip/sys_proto.h
+++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h
@@ -7,4 +7,27 @@
#ifndef _ASM_ARCH_SYS_PROTO_H
#define _ASM_ARCH_SYS_PROTO_H
+#ifdef CONFIG_ROCKCHIP_RK3288
+#include <asm/armv7.h>
+
+static void configure_l2ctlr(void)
+{
+ uint32_t l2ctlr;
+
+ l2ctlr = read_l2ctlr();
+ l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
+
+ /*
+ * Data RAM write latency: 2 cycles
+ * Data RAM read latency: 2 cycles
+ * Data RAM setup latency: 1 cycle
+ * Tag RAM write latency: 1 cycle
+ * Tag RAM read latency: 1 cycle
+ * Tag RAM setup latency: 1 cycle
+ */
+ l2ctlr |= (1 << 3 | 1 << 0);
+ write_l2ctlr(l2ctlr);
+}
+#endif /* CONFIG_ROCKCHIP_RK3288 */
+
#endif /* _ASM_ARCH_SYS_PROTO_H */
diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c
b/arch/arm/mach-rockchip/rk3288-board-spl.c
index 8a1066c..23af653 100644
--- a/arch/arm/mach-rockchip/rk3288-board-spl.c
+++ b/arch/arm/mach-rockchip/rk3288-board-spl.c
@@ -13,7 +13,6 @@
#include <malloc.h>
#include <ram.h>
#include <spl.h>
-#include <asm/armv7.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/bootrom.h>
@@ -21,6 +20,7 @@
#include <asm/arch/hardware.h>
#include <asm/arch/periph.h>
#include <asm/arch/sdram.h>
+#include <asm/arch/sys_proto.h>
#include <asm/arch/timer.h>
#include <dm/pinctrl.h>
#include <dm/root.h>
@@ -81,25 +81,6 @@ u32 spl_boot_mode(const u32 boot_device)
return MMCSD_MODE_RAW;
}
-static void configure_l2ctlr(void)
-{
- uint32_t l2ctlr;
-
- l2ctlr = read_l2ctlr();
- l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */
-
- /*
- * Data RAM write latency: 2 cycles
- * Data RAM read latency: 2 cycles
- * Data RAM setup latency: 1 cycle
- * Tag RAM write latency: 1 cycle
- * Tag RAM read latency: 1 cycle
- * Tag RAM setup latency: 1 cycle
- */
- l2ctlr |= (1 << 3 | 1 << 0);
- write_l2ctlr(l2ctlr);
-}
-
#ifdef CONFIG_SPL_MMC_SUPPORT
static int configure_emmc(struct udevice *pinctrl)
{
--
2.7.4
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