Rockchip SoCs bootrom design is like this:
- First 2KB or 4KB internal memory is for bootrom stack and heap;
- Then the first 4-byte suppose to be a TAG like 'RK33';
- The the following memory address end with '0004' is the first
instruction load and running by bootrom;
Let's use the boot0 hook to reserve the first 4-byte tag for all
the Rockchip SoCs.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems>
[Commit message:]
Signed-off-by: Kever Yang <kever.y...@rock-chips.com>
Signed-off-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com>
---
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/Kconfig | 1 +
arch/arm/mach-rockchip/Kconfig | 2 --
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 5d1ce3e..d5050d0 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1109,6 +1109,7 @@ config ARCH_ROCKCHIP
select DM_USB if USB
select DM_PWM
select DM_REGULATOR
+ select ENABLE_ARM_SOC_BOOT0_HOOK
imply CMD_FASTBOOT
imply FASTBOOT
imply FAT_WRITE
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index d9b25d5..31e9864 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -74,7 +74,6 @@ config ROCKCHIP_RK3368
imply SPL_SEPARATE_BSS
imply SPL_SERIAL_SUPPORT
imply TPL_SERIAL_SUPPORT
- select ENABLE_ARM_SOC_BOOT0_HOOK
select DEBUG_UART_BOARD_INIT
select SYS_NS16550
help
@@ -112,7 +111,6 @@ config ROCKCHIP_RK3399
select SPL_SEPARATE_BSS
select SPL_SERIAL_SUPPORT
select SPL_DRIVERS_MISC_SUPPORT
- select ENABLE_ARM_SOC_BOOT0_HOOK
select DEBUG_UART_BOARD_INIT
help
The Rockchip RK3399 is a ARM-based SoC with a dual-core Cortex-A72
--
2.1.4
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