Adjust the code structure, detail the function module function,
remove the redundancy code.
Signed-off-by: Bao Xiaowei <xiaowei....@nxp.com>
---
arch/powerpc/include/asm/fsl_pci.h | 1 +
drivers/pci/fsl_pci_init.c | 150 ++++++++++++++++++++-----------------
2 files changed, 83 insertions(+), 68 deletions(-)
diff --git a/arch/powerpc/include/asm/fsl_pci.h
b/arch/powerpc/include/asm/fsl_pci.h
index 970f3a48d5..70a5461709 100644
--- a/arch/powerpc/include/asm/fsl_pci.h
+++ b/arch/powerpc/include/asm/fsl_pci.h
@@ -24,6 +24,7 @@
#define PCI_LTSSM 0x404 /* PCIe Link Training, Status State Machine */
#define PCI_LTSSM_L0 0x16 /* L0 state */
+#define PCI_LTSSM_L0_PEX_REV3 0x11 /* L0 state for pex rev3*/
int fsl_setup_hose(struct pci_controller *hose, unsigned long addr);
int fsl_is_pci_agent(struct pci_controller *hose);
diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index af20cf0f3e..be57e53811 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -39,6 +39,8 @@ DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CONFIG_SYS_PCI64_MEMORY_BUS)
#define CONFIG_SYS_PCI64_MEMORY_BUS (64ull*1024*1024*1024)
#endif
+#define PEX_CSR0_LTSSM_MASK 0xFC
+#define PEX_CSR0_LTSSM_SHIFT 2
/* Setup one inbound ATMU window.
*
@@ -290,6 +292,80 @@ static void fsl_pcie_boot_master_release_slave(int port)
}
#endif
+static int fsl_is_pex_rev_3(struct fsl_pci_info *pci_info)
+{
+ u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
+ ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
+ u32 block_rev;
+
+ block_rev = in_be32(&pci->block_rev1);
+ if (block_rev >= PEX_IP_BLK_REV_3_0)
+ return 1;
+
+ return 0;
+}
+
+static int fsl_get_ltssm(struct pci_controller *hose,
+ struct fsl_pci_info *pci_info)
+{
+ u16 ltssm = 0;
+ pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
+ u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
+ ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
+
+ if (fsl_is_pex_rev_3(pci_info))
+ ltssm = (in_be32(&pci->pex_csr0)
+ & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
+ else
+ pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
+
+ return ltssm;
+}
+
+static int fsl_pci_link_up(struct pci_controller *hose,
+ struct fsl_pci_info *pci_info)
+{
+ int enabled = 0;
+ u16 ltssm;
+ int i, pci_ltssm_l0;
+
+ if (fsl_is_pex_rev_3(pci_info))
+ pci_ltssm_l0 = PCI_LTSSM_L0_PEX_REV3;
+ else
+ pci_ltssm_l0 = PCI_LTSSM_L0;
+
+ ltssm = fsl_get_ltssm(hose, pci_info);
+
+ if (ltssm == pci_ltssm_l0) {
+ enabled = 1;
+ } else {
+ for (i = 0; i < 100 && ltssm < pci_ltssm_l0; i++) {
+ ltssm = fsl_get_ltssm(hose, pci_info);
+ udelay(1000);
+ }
+ enabled = ltssm >= pci_ltssm_l0;
+ }
+
+ return enabled;
+}
+
+#if defined(CONFIG_FSL_PCIE_RESET) || \
+ defined(CONFIG_SYS_P4080_ERRATUM_PCIE_A003)
+static void fsl_do_pcie_reset(struct fsl_pci_info *pci_info)
+{
+ u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
+ ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)cfg_addr;
+
+ /* assert PCIe reset */
+ setbits_be32(&pci->pdb_stat, 0x08000000);
+ (void) in_be32(&pci->pdb_stat);
+ udelay(1000);
+ /* clear PCIe reset */
+ clrbits_be32(&pci->pdb_stat, 0x08000000);
+ asm("sync;isync");
+}
+#endif
+
void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
{
u32 cfg_addr = (u32)&((ccsr_fsl_pci_t *)pci_info->regs)->cfg_addr;
@@ -298,7 +374,6 @@ void fsl_pci_init(struct pci_controller *hose, struct
fsl_pci_info *pci_info)
u32 temp32;
u32 block_rev;
int enabled, r, inbound = 0;
- u16 ltssm;
u8 temp8, pcie_cap;
int pcie_cap_pos;
int pci_dcr;
@@ -438,63 +513,12 @@ void fsl_pci_init(struct pci_controller *hose, struct
fsl_pci_info *pci_info)
udelay(1);
#endif
if (pcie_cap == PCI_CAP_ID_EXP) {
- if (block_rev >= PEX_IP_BLK_REV_3_0) {
-#define PEX_CSR0_LTSSM_MASK 0xFC
-#define PEX_CSR0_LTSSM_SHIFT 2
- ltssm = (in_be32(&pci->pex_csr0)
- & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
- enabled = (ltssm == 0x11) ? 1 : 0;
#ifdef CONFIG_FSL_PCIE_RESET
- int i;
- /* assert PCIe reset */
- setbits_be32(&pci->pdb_stat, 0x08000000);
- (void) in_be32(&pci->pdb_stat);
- udelay(1000);
- /* clear PCIe reset */
- clrbits_be32(&pci->pdb_stat, 0x08000000);
- asm("sync;isync");
- for (i = 0; i < 100 && ltssm < PCI_LTSSM_L0; i++) {
- pci_hose_read_config_word(hose, dev, PCI_LTSSM,
- <ssm);
- udelay(1000);
- }
+ fsl_do_pcie_reset(pci_info);
+ pci_hose_write_config_dword(hose, dev,
+ PCI_BASE_ADDRESS_0, pcicsrbar);
#endif
- } else {
- /* pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm); */
- /* enabled = ltssm >= PCI_LTSSM_L0; */
- pci_hose_read_config_word(hose, dev, PCI_LTSSM, <ssm);
- enabled = ltssm >= PCI_LTSSM_L0;
-
-#ifdef CONFIG_FSL_PCIE_RESET
- if (ltssm == 1) {
- int i;
- debug("....PCIe link error. " "LTSSM=0x%02x.", ltssm);
- /* assert PCIe reset */
- setbits_be32(&pci->pdb_stat, 0x08000000);
- (void) in_be32(&pci->pdb_stat);
- udelay(100);
- debug(" Asserting PCIe reset @%p = %x\n",
- &pci->pdb_stat, in_be32(&pci->pdb_stat));
- /* clear PCIe reset */
- clrbits_be32(&pci->pdb_stat, 0x08000000);
- asm("sync;isync");
- for (i=0; i<100 && ltssm < PCI_LTSSM_L0; i++) {
- pci_hose_read_config_word(hose, dev, PCI_LTSSM,
- <ssm);
- udelay(1000);
- debug("....PCIe link error. "
- "LTSSM=0x%02x.\n", ltssm);
- }
- enabled = ltssm >= PCI_LTSSM_L0;
-
- /* we need to re-write the bar0 since a reset will
- * clear it
- */
- pci_hose_write_config_dword(hose, dev,
- PCI_BASE_ADDRESS_0, pcicsrbar);
- }
-#endif
- }
+ enabled = fsl_pci_link_up(hose, pci_info);
#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
if (enabled == 0) {
@@ -502,19 +526,9 @@ void fsl_pci_init(struct pci_controller *hose, struct
fsl_pci_info *pci_info)
temp32 = in_be32(&srds_regs->srdspccr0);
if ((temp32 >> 28) == 3) {
- int i;
-
out_be32(&srds_regs->srdspccr0, 2 << 28);
- setbits_be32(&pci->pdb_stat, 0x08000000);
- in_be32(&pci->pdb_stat);
- udelay(100);
- clrbits_be32(&pci->pdb_stat, 0x08000000);
- asm("sync;isync");
- for (i=0; i < 100 && ltssm < PCI_LTSSM_L0; i++)
{
- pci_hose_read_config_word(hose, dev,
PCI_LTSSM, <ssm);
- udelay(1000);
- }
- enabled = ltssm >= PCI_LTSSM_L0;
+ fsl_do_pcie_reset(pci_info);
+ enabled = fsl_pci_link_up(hose, pci_info);
}
}
#endif
--
2.14.1
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
