The rk3328 soc has two gmac controllers, one is gmac2io,
the other is gmac2phy. We use the gmac2io rgmii interface
for 1000M phy here.
Signed-off-by: David Wu <david...@rock-chips.com>
---
Changes in v2:
- New patch
drivers/clk/rockchip/clk_rk3328.c | 20 ++++++++++++++++++++
include/dt-bindings/clock/rk3328-cru.h | 6 +++---
2 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/rockchip/clk_rk3328.c
b/drivers/clk/rockchip/clk_rk3328.c
index 540d910..0940474 100644
--- a/drivers/clk/rockchip/clk_rk3328.c
+++ b/drivers/clk/rockchip/clk_rk3328.c
@@ -13,6 +13,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/cru_rk3328.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/grf_rk3328.h>
#include <asm/io.h>
#include <dm/lists.h>
#include <dt-bindings/clock/rk3328-cru.h>
@@ -393,6 +394,22 @@ static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru,
ulong clk_id, uint hz)
return DIV_TO_RATE(GPLL_HZ, src_clk_div);
}
+static int rockchip_mac_set_clk(struct rk3328_cru *cru,
+ int periph, uint freq)
+{
+ struct rk3328_grf_regs *grf;
+
+ grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+ /* Assuming mac_clk is fed by an external clock */
+ rk_clrsetreg(&grf->soc_con[4], BIT(14),
+ BIT(14));
+
+ rk_clrsetreg(&grf->mac_con[1], BIT(10),
+ BIT(10));
+
+ return 0;
+}
+
static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id)
{
u32 div, con, con_id;
@@ -558,6 +575,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong
rate)
case SCLK_I2C3:
ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate);
break;
+ case SCLK_MAC2IO:
+ ret = rockchip_mac_set_clk(priv->cru, clk->id, rate);
+ break;
case SCLK_PWM:
ret = rk3328_pwm_set_clk(priv->cru, rate);
break;
diff --git a/include/dt-bindings/clock/rk3328-cru.h
b/include/dt-bindings/clock/rk3328-cru.h
index 6d8bf13..cdc0b33 100644
--- a/include/dt-bindings/clock/rk3328-cru.h
+++ b/include/dt-bindings/clock/rk3328-cru.h
@@ -86,6 +86,9 @@
#define SCLK_USB3OTG_SUSPEND 97
#define SCLK_REF_USB3OTG_SRC 98
#define SCLK_MAC2IO_SRC 99
+#define SCLK_MAC2IO 100
+#define SCLK_MAC2PHY 101
+#define SCLK_MAC2IO_EXT 102
/* dclk gates */
#define DCLK_LCDC 180
@@ -199,9 +202,6 @@
#define CLK_NR_CLKS (HCLK_HDCP + 1)
-#define SCLK_MAC2IO 0
-#define SCLK_MAC2PHY 1
-
#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
/* soft-reset indices */
--
2.7.4
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