On Thu, Oct 26, 2017 at 01:23:19PM +0200, [email protected] wrote: > From: Patrice Chotard <[email protected]> > > Fix clock division factor initialization for RCC_PLLCFGR > registers. > > PLLR bits (bit 31-28) in RCC_PLLCFGR must not be cleared, > it's a forbidden value. So update RCC_PLLCFGR using > clrsetbits_le32() to set only necessary bits fields. > > Signed-off-by: Patrice Chotard <[email protected]> > Reviewed-by: Simon Glass <[email protected]>
Applied to u-boot/master, thanks! -- Tom
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