On 21.11.2017 21:33, Paul Burton wrote: > On some systems aligning PCI memory to a 1MB boundary every time a > bridge is encountered may lead to exhausting the available memory space > before all devices have been assigned addresses. > > For example on the MIPS Boston development board we have an Intel EG20T > Platform Controller Hub connected to a Xilinx AXI to PCIe root port > which is only assigned a 1MB memory region. The Intel EG20T contains a > bridge device beneath which all of its peripheral devices can be found, > and that bridge device contains a ROM. If we align to 1MB when we > encounter each bridge device we therefore do something like this: > > - Start with bus_lower at 0x16000000. > > - Find the Xilinx root bridge, which has no visible BARs so we do very > little to it. > > - Probe the bus beneath the Xilinx bridge device, aligning bus_lower > to a 1MB boundary first. That leaves it still at 0x16000000. > > - Find the EG20T bridge device, which we find has a 64KiB ROM. We > assign it the address range 0x16000000-0x1600ffff which leaves > bus_lower at 0x16010000. > > - Probe the bus beneath the EG20T bridge device, aligning bus_lower to > a 1MB boundary first. This leaves bus_lower at 0x16100000, which is > the end of the available memory space. > > - Find the various peripheral devices the EG20T contains, but fail to > assign any memory space to them since bus_lower is at the end of the > memory space available to the PCI bus. > > This patch allows that 1MB alignment to be changed or disabled via > Kconfig, so that systems such as this can select an alignment which > works for them. > > Signed-off-by: Paul Burton <[email protected]> > Cc: Daniel Schwierzeck <[email protected]> > Cc: Simon Glass <[email protected]> > Cc: [email protected] > Signed-off-by: Paul Burton <[email protected]> > --- > > drivers/pci/Kconfig | 7 +++++++ > drivers/pci/pci_auto.c | 24 ++++++++++++++++-------- > 2 files changed, 23 insertions(+), 8 deletions(-) >
Reviewed-by: Daniel Schwierzeck <[email protected]> -- - Daniel
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