> There is a fixed div-2 between PLL and clk_ddr/clk_ddrphy, > so we need to double to pll output and then ddr can work > in correct frequency. > > Signed-off-by: Kever Yang <kever.y...@rock-chips.com> > --- > > arch/arm/mach-rockchip/rk3036/sdram_rk3036.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) >
Acked-by: Philipp Tomsich <philipp.toms...@theobroma-systems.com> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
