On 12/12/2017 11:41 AM, York Sun wrote: > Increase setup, assertion and hold time related to chip-select signal. > Additional delay is needed for the signal to propogate through FPGA. > This adjustment slightly increase the read and write cycle but has no > impact on burst read or write. > > Signed-off-by: York Sun <[email protected]> > ---
Applied to fsl-qoriq master. York _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
