SPEAr310 and SPEAr320 SoCs contain an EMI controller to interface Paraller NOR flashes. This patch adds the support for this IP
The standard CFI driver is used to interface with NOR flashes Signed-off-by: Vipin <[email protected]> --- board/spear/common/spr_misc.c | 60 ++++++++++++++++++++++++++++++++++ include/asm-arm/arch-spear/spr_emi.h | 54 ++++++++++++++++++++++++++++++ 2 files changed, 114 insertions(+), 0 deletions(-) create mode 100644 include/asm-arm/arch-spear/spr_emi.h diff --git a/board/spear/common/spr_misc.c b/board/spear/common/spr_misc.c index 9a6260f..08fb0bc 100755 --- a/board/spear/common/spr_misc.c +++ b/board/spear/common/spr_misc.c @@ -26,6 +26,7 @@ #include <i2c.h> #include <net.h> #include <asm/io.h> +#include <asm/arch/spr_emi.h> #include <asm/arch/spr_xloader_table.h> #include <asm/arch/spr_defs.h> @@ -78,6 +79,62 @@ int misc_init_r(void) return 0; } +#ifdef CONFIG_SPEAR_EMI +struct cust_emi_para { + unsigned int tap; + unsigned int tsdp; + unsigned int tdpw; + unsigned int tdpr; + unsigned int tdcs; + unsigned int control; +}; Maybe this should be packed ? + +/* EMI timing setting of m28w640hc of linux kernel */ +const struct cust_emi_para emi_timing_m28w640hc = { + .tap = 0x10, + .tsdp = 0x05, + .tdpw = 0x0a, + .tdpr = 0x0a, + .tdcs = 0x05, .control ? If this is a read-only register, add a comment. Tom _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
