This is useful to make sure no stale data exists in caches after bootloaders. The worst thing could be some lines of cache were locked in a bootloader for example during DDR recalibration and never unlocked. This may lead to really unpredictable issues later down the line.
Signed-off-by: Eugeniy Paltsev <[email protected]> --- arch/arc/lib/start.S | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index 95d64f9..0d72fe7 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -44,6 +44,14 @@ ENTRY(_start) #endif sr r5, [ARC_AUX_IC_CTRL] + mov r5, 1 + sr r5, [ARC_AUX_IC_IVIC] + ; As per ARC HS databook (see chapter 5.3.3.2) + ; it is required to add 3 NOPs after each write to IC_IVIC. + nop + nop + nop + 1: ; Disable/enable D-cache according to configuration lr r5, [ARC_BCR_DC_BUILD] @@ -57,6 +65,10 @@ ENTRY(_start) #endif sr r5, [ARC_AUX_DC_CTRL] + mov r5, 1 + sr r5, [ARC_AUX_DC_IVDC] + + 1: #ifdef CONFIG_ISA_ARCV2 ; Disable System-Level Cache (SLC) -- 2.9.3 _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
