On 10/01/2018 06:20, Peng Fan wrote:
> The MIB RAM and FIFO receive start register does not exist on
> i.MX8M. Accessing these register will cause system hang.
>
> Signed-off-by: Peng Fan <peng....@nxp.com>
> Acked-by: Joe Hershberger <joe.hershber...@ni.com>
> Reviewed-by: Stefano Babic <sba...@denx.de>
> Reviewed-by: Fabio Estevam <fabio.este...@nxp.com>
> ---
> drivers/net/fec_mxc.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
> index 433e19f0f8..4cbc8cbbfd 100644
> --- a/drivers/net/fec_mxc.c
> +++ b/drivers/net/fec_mxc.c
> @@ -562,8 +562,8 @@ static int fec_init(struct eth_device *dev, bd_t *bd)
> writel(0x00000000, &fec->eth->gaddr1);
> writel(0x00000000, &fec->eth->gaddr2);
>
> - /* Do not access reserved register for i.MX6UL */
> - if (!is_mx6ul() && !is_mx6ull()) {
> + /* Do not access reserved register */
> + if (!is_mx6ul() && !is_mx6ull() && !is_mx8m()) {
> /* clear MIB RAM */
> for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
> writel(0, i);
>
Reviewed-by: Stefano Babic <sba...@denx.de>
Best regards,
Stefano Babic
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