Signed-off-by: Álvaro Fernández Rojas <nolt...@gmail.com>
---
 v2: no changes

 arch/mips/dts/brcm,bcm6328.dtsi | 30 ++++++++++++++++++++++++++++++
 include/configs/bmips_bcm6328.h |  7 +++++++
 2 files changed, 37 insertions(+)

diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi
index 67d9278be4..4fbbcec153 100644
--- a/arch/mips/dts/brcm,bcm6328.dtsi
+++ b/arch/mips/dts/brcm,bcm6328.dtsi
@@ -153,6 +153,36 @@
                        #power-domain-cells = <1>;
                };
 
+               ehci: usb-controller@10002500 {
+                       compatible = "brcm,bcm6328-ehci", "generic-ehci";
+                       reg = <0x10002500 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               ohci: usb-controller@10002600 {
+                       compatible = "brcm,bcm6328-ohci", "generic-ohci";
+                       reg = <0x10002600 0x100>;
+                       phys = <&usbh>;
+                       big-endian;
+
+                       status = "disabled";
+               };
+
+               usbh: usb-phy@10002700 {
+                       compatible = "brcm,bcm6328-usbh";
+                       reg = <0x10002700 0x38>;
+                       #phy-cells = <0>;
+                       clocks = <&periph_clk BCM6328_CLK_USBH>;
+                       clock-names = "usbh";
+                       power-domains = <&periph_pwr BCM6328_PWR_USBH>;
+                       resets = <&periph_rst BCM6328_RST_USBH>;
+
+                       status = "disabled";
+               };
+
                memory-controller@10003000 {
                        compatible = "brcm,bcm6328-mc";
                        reg = <0x10003000 0x864>;
diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h
index 41c7838a23..2cb9b5540e 100644
--- a/include/configs/bmips_bcm6328.h
+++ b/include/configs/bmips_bcm6328.h
@@ -14,6 +14,13 @@
 #define CONFIG_NR_DRAM_BANKS           1
 #define CONFIG_SYS_SDRAM_BASE          0x80000000
 
+/* USB */
+#define CONFIG_EHCI_DESC_BIG_ENDIAN
+#define CONFIG_EHCI_MMIO_BIG_ENDIAN
+#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
+#define CONFIG_USB_OHCI_NEW
+
 /* U-Boot */
 #define CONFIG_SYS_LOAD_ADDR           CONFIG_SYS_SDRAM_BASE + 0x100000
 
-- 
2.11.0

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