The device-tree node for the PMU clk controller assigns to its parent
(i.e. PLL_PPLL) even though this clock currently is set up statically
by an init-function.

In order to avoid unexpected failures, a simple implementation of
set_rate (which accepts requests, but notifies the caller of the
preset frequency in its return value) and get_rate (which always
returns the preset frequency) are added.

Note that this is required for the RK808 PMIC to probe successfully on
the RK3399-Q7, following the support for the assigned-clocks property.

References: commit f4fcba5c5baa ("clk: implement clk_set_defaults()")
Signed-off-by: Philipp Tomsich <>
Tested-by: Klaus Goger <>

 drivers/clk/rockchip/clk_rk3399.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c 
index 42926ba..37237e3 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -1236,6 +1236,8 @@ static ulong rk3399_pmuclk_get_rate(struct clk *clk)
        ulong rate = 0;
        switch (clk->id) {
+       case PLL_PPLL:
+               return PPLL_HZ;
        case PCLK_RKPWM_PMU:
                rate = rk3399_pwm_get_clk(priv->pmucru);
@@ -1257,7 +1259,13 @@ static ulong rk3399_pmuclk_set_rate(struct clk *clk, 
ulong rate)
        ulong ret = 0;
        switch (clk->id) {
+       case PLL_PPLL:
+               /*
+                * This has already been set up and we don't want/need
+                * to change it here.  Accept the request though, as the
+                * device-tree has this in an 'assigned-clocks' list.
+                */
+               return PPLL_HZ;
        case SCLK_I2C0_PMU:
        case SCLK_I2C4_PMU:
        case SCLK_I2C8_PMU:

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