On Sun, Feb 25, 2018 at 11:43:13AM +0100, Dr. Philipp Tomsich wrote: > Tom, > > we have additional fixes ready for you: > * the TPL-build process for the Vyasa board was fixed by Jagan (by > providing the correct TEXT_BASE) > * a regression on Ethernet for the RK3399 and RK3368 has been resolved > by adding support for its clocks > * a regression on PMIC probing on the RK399 has been resolved by adding > support for the assigned-clocks of the PMUCRU > > Travis report is at > https://travis-ci.org/ptomsich/u-boot-rockchip/builds/345699336 > > Thanks, > Philipp. > > > The following changes since commit 0bb430c8494e26e8d258cf6957cdd39d2ce4f309: > > Merge git://git.denx.de/u-boot-video (2018-02-24 08:02:17 -0500) > > are available in the git repository at: > > git://git.denx.de/u-boot-rockchip.git master > > for you to fetch changes up to 434d5a00a4578f826e7e2cef29bf2388dd760a88: > > rockchip: clk: rk3399: handle set_rate/get_rate for PLL_PPLL (2018-02-24 > 18:50:03 +0100) >
Applied to u-boot/master, thanks! -- Tom
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