> > Dear Hannes, Dear Jaehoon, > >> Instead, its bit is used to other purpose. > > > > Please explain me more about this other purpose, > > maybe i'm missunterstand here something. > > SD Host Controller has the HOST Controller register (Offset 0x28). > BIT is "High speed enable". > - BIT : 0 - Normal Speed mode > - BIT : 1 - High Speed mode. > This bit is "RW" attribute. > > And Samsung SoC also has the HOST Controller register (offset 0x28). > BIT is "Output Edge Inversion". > - BIT : 0 - Rising edge output. > - BIT : 1 - Falling edge output. > > "High speed enable" bit is standard. but Samsung SoC is using it for other purpose. > So I had added the quirks for SDHCI_QUIRK_NO_HISPD_BIT. > It means that there is no 'high speed bit'.
OK. Many thanks for clarifying this. I took a look to the ZYNQ TRM and an the register 0x28 of the sdhci controller, here we have standard behaviour where bit controls the high speed stuff. The conclusion of this is, that the "zynq_sdhci.c" uses the SDHCI_QUIRK_NO_HISPD_BIT wrong and this must be fixed. I did grep for the "CONFIG_ZYNQ_HISPD_BROKEN" within source tree and observed that nobody or no boards except mine uses this #define. This would explain that, i call it this bug, is unnoticed yet. > > If your patch is applied, Samsung SoC can work the unexpected behavior. > > If your ip also doesn't use this bit, then no problem. > But your patch tried to use the other purpose. OK. > > > > > Maybe i've to introduce some new quirk, which tells the ip-core and the > > other layers> above not using HIGH_SPEED. But i think still this is the right one ... > > Well, i don't want to add the new quirk, if there is a solution not to add the quriks. > If really needs, you need to add the SDHCI_QUIRK_BROKEN_HISPD_MODE. > > #define SDHCI_QUIRK_BROKEN_HISPD_MODE (1 << 5) OK. But i fear that we've to introduce this new quirk. Because in real life mistakes in hardware-design (in this case chip design) happen and we software guys have to workaround them. https://www.xilinx.com/support/answers/59999.html > > and change from SDHCI_QUIRK_NO_HSIPD_BIT to SDHCI_QUIRK_BROKEN_HISPD_MODE in > zynq_sdhci.c. I will do so. I will also send some V2 of my patch, with doing: - add this new QUIRK - fix the zynq_sdhci.c - consider this quirk in the host_cap > > I will update the descriptions about quirks. Because it can be confused what > purpose is used. Great, so it will be more readable in the future. > > Best Regards, > Jaehoon Chung cheers, Hannes _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot