This patch enables ethernet support for ls1012a2g5rdb.
Signed-off-by: Calvin Johnson <calvin.john...@nxp.com>
Signed-off-by: Bhaskar Upadhaya <bhaskar.upadh...@nxp.com>
---
Changes in v3:
-Update Kconfig
-Update header file location to include/net/pfe_eth
-Prefix CONFIG_PFE_ to appropriate macros
-Indent properly
Changes in v2:
-New patch added to series to enable ethernet support for
ls1012a2g5rdb
board/freescale/ls1012ardb/Kconfig | 30 +++++++++++++++++++++++++
board/freescale/ls1012ardb/eth.c | 45 +++++++++++++++++++++++++++++++-------
2 files changed, 67 insertions(+), 8 deletions(-)
diff --git a/board/freescale/ls1012ardb/Kconfig
b/board/freescale/ls1012ardb/Kconfig
index af35a01..493d477 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -59,6 +59,36 @@ config SYS_SOC
config SYS_CONFIG_NAME
default "ls1012a2g5rdb"
+if FSL_PFE
+
+config BOARD_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select PHYLIB
+ imply CONFIG_PHYLIB_10G
+ imply CONFIG_PHY_AQUANTIA
+
+config SYS_LS_PFE_FW_ADDR
+ hex "Flash address of PFE firmware"
+ default 0x40a00000
+
+config DDR_PFE_PHYS_BASEADDR
+ hex "PFE DDR physical base address"
+ default 0x03800000
+
+config DDR_PFE_BASEADDR
+ hex "PFE DDR base address"
+ default 0x83800000
+
+config PFE_EMAC1_PHY_ADDR
+ hex "PFE DDR base address"
+ default 0x2
+
+config PFE_EMAC2_PHY_ADDR
+ hex "PFE DDR base address"
+ default 0x1
+
+endif
+
source "board/freescale/common/Kconfig"
endif
diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c
index e6379a3..8e6cd0a 100644
--- a/board/freescale/ls1012ardb/eth.c
+++ b/board/freescale/ls1012ardb/eth.c
@@ -26,6 +26,7 @@
static inline void ls1012ardb_reset_phy(void)
{
+#ifdef CONFIG_TARGET_LS1012ARDB
/* Through reset IO expander reset both RGMII and SGMII PHYs */
i2c_reg_write(I2C_MUX_IO2_ADDR, 6, __PHY_MASK);
i2c_reg_write(I2C_MUX_IO2_ADDR, 2, __PHY_ETH2_MASK);
@@ -34,6 +35,7 @@ static inline void ls1012ardb_reset_phy(void)
mdelay(10);
i2c_reg_write(I2C_MUX_IO2_ADDR, 2, 0xFF);
mdelay(50);
+#endif
}
int pfe_eth_board_init(struct udevice *dev)
@@ -42,6 +44,11 @@ int pfe_eth_board_init(struct udevice *dev)
struct mii_dev *bus;
struct pfe_mdio_info mac_mdio_info;
struct pfe_eth_dev *priv = dev_get_priv(dev);
+ struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
+
+ int srds_s1 = in_be32(&gur->rcwsr[4]) &
+ FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
+ srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
if (!init_done) {
ls1012ardb_reset_phy();
@@ -59,14 +66,36 @@ int pfe_eth_board_init(struct udevice *dev)
pfe_set_mdio(priv->gemac_port,
miiphy_get_dev_by_name(DEFAULT_PFE_MDIO_NAME));
- if (!priv->gemac_port) {
- /* MAC1 */
- pfe_set_phy_address_mode(priv->gemac_port, EMAC1_PHY_ADDR,
- PHY_INTERFACE_MODE_SGMII);
- } else {
- /* MAC2 */
- pfe_set_phy_address_mode(priv->gemac_port, EMAC2_PHY_ADDR,
- PHY_INTERFACE_MODE_RGMII_TXID);
+ switch (srds_s1) {
+ case 0x3508:
+ if (!priv->gemac_port) {
+ /* MAC1 */
+ pfe_set_phy_address_mode(priv->gemac_port,
+ CONFIG_PFE_EMAC1_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII);
+ } else {
+ /* MAC2 */
+ pfe_set_phy_address_mode(priv->gemac_port,
+ CONFIG_PFE_EMAC2_PHY_ADDR,
+ PHY_INTERFACE_MODE_RGMII_TXID);
+ }
+ break;
+ case 0x2208:
+ if (!priv->gemac_port) {
+ /* MAC1 */
+ pfe_set_phy_address_mode(priv->gemac_port,
+ CONFIG_PFE_EMAC1_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII_2500);
+ } else {
+ /* MAC2 */
+ pfe_set_phy_address_mode(priv->gemac_port,
+ CONFIG_PFE_EMAC2_PHY_ADDR,
+ PHY_INTERFACE_MODE_SGMII_2500);
+ }
+ break;
+ default:
+ printf("unsupported SerDes PRCTL= %d\n", srds_s1);
+ break;
}
return 0;
}
--
2.7.4
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