From: Nitin Jain <nitin.j...@xilinx.com>

This patch is used for disable the strict alignment of data
to avoid the memory alignment issues.

Also setup this option for Xilinx Zynq.

Signed-off-by: Nitin Jain <nit...@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva...@xilinx.com>
Signed-off-by: Michal Simek <michal.si...@xilinx.com>
---

Not sure if there is any side effects but our tests don't show up any
issue with disabling this bit.

---
 arch/arm/Kconfig           | 1 +
 arch/arm/cpu/armv7/Kconfig | 6 ++++++
 arch/arm/cpu/armv7/start.S | 2 ++
 3 files changed, 9 insertions(+)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index a66d04eadfcb..4b5c64c8ba8b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -778,6 +778,7 @@ config ARCH_ZYNQ
        imply CMD_CLK
        imply FAT_WRITE
        imply CMD_SPL
+       imply ARMV7_MEM_ALIGN_DISABLE
 
 config ARCH_ZYNQMP
        bool "Xilinx ZynqMP based platform"
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index b9c4f4e79b9b..d5c0f0ebab17 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -58,4 +58,10 @@ config ARMV7_LPAE
        Say Y here to use the long descriptor page table format. This is
        required if U-Boot runs in HYP mode.
 
+config ARMV7_MEM_ALIGN_DISABLE
+       bool "Disable strict alignment of data"
+       help
+        Enabling this option disables strict alignment for armv7 by
+        setting the alignment bit in system control register of cp15.
+
 endif
diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
index 7e2695761e98..795b702a5f9c 100644
--- a/arch/arm/cpu/armv7/start.S
+++ b/arch/arm/cpu/armv7/start.S
@@ -150,7 +150,9 @@ ENTRY(cpu_init_cp15)
        mrc     p15, 0, r0, c1, c0, 0
        bic     r0, r0, #0x00002000     @ clear bits 13 (--V-)
        bic     r0, r0, #0x00000007     @ clear bits 2:0 (-CAM)
+#ifndef CONFIG_ARMV7_MEM_ALIGN_DISABLE
        orr     r0, r0, #0x00000002     @ set bit 1 (--A-) Align
+#endif
        orr     r0, r0, #0x00000800     @ set bit 11 (Z---) BTB
 #ifdef CONFIG_SYS_ICACHE_OFF
        bic     r0, r0, #0x00001000     @ clear bit 12 (I) I-cache
-- 
1.9.1

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