According to specification, CFG_PM_RXDLOZ_WAIT should be set to 0x7
when reference clock is at 25 MHz. The specification (at least the
version I have) does not mentoin the setting for 40 MHz reference
clock, but Marvell's U-Boot sets 0xC in that case.

Signed-off-by: Marek Behun <marek.be...@nic.cz>
---
 drivers/phy/marvell/comphy_a3700.c | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/phy/marvell/comphy_a3700.c 
b/drivers/phy/marvell/comphy_a3700.c
index b5f2013bbb..78caa96014 100644
--- a/drivers/phy/marvell/comphy_a3700.c
+++ b/drivers/phy/marvell/comphy_a3700.c
@@ -394,20 +394,18 @@ static int comphy_usb3_power_up(u32 lane, u32 type, u32 
speed, u32 invert)
        /*
         * 3. Check crystal jumper setting and program the Power and PLL
         * Control accordingly
+        * 4. Change RX wait
         */
        if (get_ref_clk() == 40) {
                /* 40 MHz */
                usb3_reg_set16(PWR_PLL_CTRL, 0xFCA3, 0xFFFF);
+               usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF);
        } else {
                /* 25 MHz */
                usb3_reg_set16(PWR_PLL_CTRL, 0xFCA2, 0xFFFF);
+               usb3_reg_set16(PWR_MGM_TIM1, 0x107, 0xFFFF);
        }
 
-       /*
-        * 4. Change RX wait
-        */
-       usb3_reg_set16(PWR_MGM_TIM1, 0x10C, 0xFFFF);
-
        /*
         * 5. Enable idle sync
         */
-- 
2.16.1

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