Hello Jan,

let me quote my mail to Claudio, who asked more or less the same on March 
7th(see mail below). 
Personally, hoped that someone from Intel/Altera has the guts to answer this 
question or at least the Maintainer of the socfpga.
I'm by far not good at u-boot, so it is just hacked together what was needed 
for the project so far.

If any Maintainer reads this, I suggest removing the Arria10 from the current 
master branch as it is unusable(system does not even boot) for any one the way 
it is now.

> Hello Claudio,
>
> I tried it as well and failed. My personal guess is that Altera/Intel never 
> pushed proper support into the official u-boot mainline.
> Even there master-branch 
> (https://github.com/altera-opensource/u-boot-socfpga/tree/master) does not 
> work. For "just a user" it is very frustrating getting a new board abut have 
> to use old software.
> And it seems Intel does not care in providing documentation, up-to-date 
> software or maintaining the released code.
> For example if you look closer into the source code in the 
> socfpga_v2014.10_arria10_bringup-branch there is a module called cff which 
> loads the rbf-file in early release mode.
> I could  not find anything similar in the latest branches(neither from denx 
> not altera). Also the images generated from the latest releases generates not 
> the proper format needed to boot from an Arria10.
>
> So for my needs I used 
> (https://github.com/altera-opensource/u-boot-socfpga/tree/socfpga_v2014.10_arria10_bringup)
>  which is the version used in the Altera/Intel tools But changed it to my 
> needs (loading > rbf-file, kernel and devicetree from EXT, setting u-boot 
> environment to my needs etc.) I compile everything with the toolchain from 
> yocto V2.4. and so far it works good.
> My changes are made public 
> here(https://github.com/nanosurf-ag/u-boot-socfpga) but this might still 
> subject to change.
>
> Hope this helps
> dan


Cheers
Dan
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