This platform has been marked as orphaned since September 2013, remove.

Signed-off-by: Tom Rini <tr...@konsulko.com>
---
 arch/arm/Kconfig                        |   6 -
 board/freescale/mx31ads/Kconfig         |  15 --
 board/freescale/mx31ads/MAINTAINERS     |   6 -
 board/freescale/mx31ads/Makefile        |   8 -
 board/freescale/mx31ads/lowlevel_init.S | 268 --------------------------------
 board/freescale/mx31ads/mx31ads.c       | 114 --------------
 board/freescale/mx31ads/u-boot.lds      | 110 -------------
 configs/mx31ads_defconfig               |  15 --
 include/configs/mx31ads.h               | 144 -----------------
 9 files changed, 686 deletions(-)
 delete mode 100644 board/freescale/mx31ads/Kconfig
 delete mode 100644 board/freescale/mx31ads/MAINTAINERS
 delete mode 100644 board/freescale/mx31ads/Makefile
 delete mode 100644 board/freescale/mx31ads/lowlevel_init.S
 delete mode 100644 board/freescale/mx31ads/mx31ads.c
 delete mode 100644 board/freescale/mx31ads/u-boot.lds
 delete mode 100644 configs/mx31ads_defconfig
 delete mode 100644 include/configs/mx31ads.h

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 1d2cbbff1ff6..9f5e1656100f 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -444,11 +444,6 @@ config TARGET_X600
        select SUPPORT_SPL
        select PL011_SERIAL
 
-config TARGET_MX31ADS
-       bool "Support mx31ads"
-       select CPU_ARM1136
-       select BOARD_EARLY_INIT_F
-
 config TARGET_MX31PDK
        bool "Support mx31pdk"
        select BOARD_LATE_INIT
@@ -1322,7 +1317,6 @@ source "board/freescale/ls1046ardb/Kconfig"
 source "board/freescale/ls1012aqds/Kconfig"
 source "board/freescale/ls1012ardb/Kconfig"
 source "board/freescale/ls1012afrdm/Kconfig"
-source "board/freescale/mx31ads/Kconfig"
 source "board/freescale/mx31pdk/Kconfig"
 source "board/freescale/mx35pdk/Kconfig"
 source "board/freescale/s32v234evb/Kconfig"
diff --git a/board/freescale/mx31ads/Kconfig b/board/freescale/mx31ads/Kconfig
deleted file mode 100644
index eeeb6f490fd2..000000000000
--- a/board/freescale/mx31ads/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_MX31ADS
-
-config SYS_BOARD
-       default "mx31ads"
-
-config SYS_VENDOR
-       default "freescale"
-
-config SYS_SOC
-       default "mx31"
-
-config SYS_CONFIG_NAME
-       default "mx31ads"
-
-endif
diff --git a/board/freescale/mx31ads/MAINTAINERS 
b/board/freescale/mx31ads/MAINTAINERS
deleted file mode 100644
index 5f6ec268c7e1..000000000000
--- a/board/freescale/mx31ads/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-MX31ADS BOARD
-#M:    (resigned) Guennadi Liakhovetski <g.liakhovet...@gmx.de>
-S:     Orphan (since 2013-09)
-F:     board/freescale/mx31ads/
-F:     include/configs/mx31ads.h
-F:     configs/mx31ads_defconfig
diff --git a/board/freescale/mx31ads/Makefile b/board/freescale/mx31ads/Makefile
deleted file mode 100644
index 5e1440d59668..000000000000
--- a/board/freescale/mx31ads/Makefile
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Copyright (C) 2008, Guennadi Liakhovetski <l...@denx.de>
-#
-# SPDX-License-Identifier:     GPL-2.0+
-#
-
-obj-y  := mx31ads.o
-obj-y  += lowlevel_init.o
diff --git a/board/freescale/mx31ads/lowlevel_init.S 
b/board/freescale/mx31ads/lowlevel_init.S
deleted file mode 100644
index fcb5549d7741..000000000000
--- a/board/freescale/mx31ads/lowlevel_init.S
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Copyright (C) 2008, Guennadi Liakhovetski <l...@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <asm/arch/imx-regs.h>
-
-.macro REG reg, val
-       ldr r2, =\reg
-       ldr r3, =\val
-       str r3, [r2]
-.endm
-
-.macro REG8 reg, val
-       ldr r2, =\reg
-       ldr r3, =\val
-       strb r3, [r2]
-.endm
-
-.macro DELAY loops
-       ldr r2, =\loops
-1:
-       subs    r2, r2, #1
-       nop
-       bcs 1b
-.endm
-
-/* RedBoot: AIPS setup - Only setup MPROTx registers.
- * The PACR default values are good.*/
-.macro init_aips
-       /*
-        * Set all MPROTx to be non-bufferable, trusted for R/W,
-        * not forced to user-mode.
-        */
-       ldr r0, =0x43F00000
-       ldr r1, =0x77777777
-       str r1, [r0, #0x00]
-       str r1, [r0, #0x04]
-       ldr r0, =0x53F00000
-       str r1, [r0, #0x00]
-       str r1, [r0, #0x04]
-
-       /*
-        * Clear the on and off peripheral modules Supervisor Protect bit
-        * for SDMA to access them. Did not change the AIPS control registers
-        * (offset 0x20) access type
-        */
-       ldr r0, =0x43F00000
-       ldr r1, =0x0
-       str r1, [r0, #0x40]
-       str r1, [r0, #0x44]
-       str r1, [r0, #0x48]
-       str r1, [r0, #0x4C]
-       ldr r1, [r0, #0x50]
-       and r1, r1, #0x00FFFFFF
-       str r1, [r0, #0x50]
-
-       ldr r0, =0x53F00000
-       ldr r1, =0x0
-       str r1, [r0, #0x40]
-       str r1, [r0, #0x44]
-       str r1, [r0, #0x48]
-       str r1, [r0, #0x4C]
-       ldr r1, [r0, #0x50]
-       and r1, r1, #0x00FFFFFF
-       str r1, [r0, #0x50]
-.endm /* init_aips */
-
-/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */
-.macro init_max
-       ldr r0, =0x43F04000
-       /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
-       ldr r1, =0x00302154
-       str r1, [r0, #0x000]        /* for S0 */
-       str r1, [r0, #0x100]        /* for S1 */
-       str r1, [r0, #0x200]        /* for S2 */
-       str r1, [r0, #0x300]        /* for S3 */
-       str r1, [r0, #0x400]        /* for S4 */
-       /* SGPCR - always park on last master */
-       ldr r1, =0x10
-       str r1, [r0, #0x010]        /* for S0 */
-       str r1, [r0, #0x110]        /* for S1 */
-       str r1, [r0, #0x210]        /* for S2 */
-       str r1, [r0, #0x310]        /* for S3 */
-       str r1, [r0, #0x410]        /* for S4 */
-       /* MGPCR - restore default values */
-       ldr r1, =0x0
-       str r1, [r0, #0x800]        /* for M0 */
-       str r1, [r0, #0x900]        /* for M1 */
-       str r1, [r0, #0xA00]        /* for M2 */
-       str r1, [r0, #0xB00]        /* for M3 */
-       str r1, [r0, #0xC00]        /* for M4 */
-       str r1, [r0, #0xD00]        /* for M5 */
-.endm /* init_max */
-
-/* RedBoot: M3IF setup */
-.macro init_m3if
-       /* Configure M3IF registers */
-       ldr r1, =0xB8003000
-       /*
-       * M3IF Control Register (M3IFCTL)
-       * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
-       * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
-       * MRRP[2] = MBX not on priority list (0 << 0)   = 0x00000000
-       * MRRP[3] = MAX1 not on priority list (0 << 0)  = 0x00000000
-       * MRRP[4] = SDMA not on priority list (0 << 0)  = 0x00000000
-       * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
-       * MRRP[6] = IPU1 on priority list (1 << 6)      = 0x00000040
-       * MRRP[7] = IPU2 not on priority list (0 << 0)  = 0x00000000
-       *                                               ------------
-       *                                                 0x00000040
-       */
-       ldr r0, =0x00000040
-       str r0, [r1]  /* M3IF control reg */
-.endm /* init_m3if */
-
-/* RedBoot: To support 133MHz DDR */
-.macro  init_drive_strength
-       /*
-        * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits
-        * in SW_PAD_CTL registers
-        */
-
-       /* SDCLK */
-       ldr r1, =0x43FAC200
-       ldr r0, [r1, #0x6C]
-       bic r0, r0, #(1 << 12)
-       str r0, [r1, #0x6C]
-
-       /* CAS */
-       ldr r0, [r1, #0x70]
-       bic r0, r0, #(1 << 22)
-       str r0, [r1, #0x70]
-
-       /* RAS */
-       ldr r0, [r1, #0x74]
-       bic r0, r0, #(1 << 2)
-       str r0, [r1, #0x74]
-
-       /* CS2 (CSD0) */
-       ldr r0, [r1, #0x7C]
-       bic r0, r0, #(1 << 22)
-       str r0, [r1, #0x7C]
-
-       /* DQM3 */
-       ldr r0, [r1, #0x84]
-       bic r0, r0, #(1 << 22)
-       str r0, [r1, #0x84]
-
-       /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */
-       ldr r2, =22     /* (0x2E0 - 0x288) / 4 = 22 */
-pad_loop:
-       ldr r0, [r1, #0x88]
-       bic r0, r0, #(1 << 22)
-       bic r0, r0, #(1 << 12)
-       bic r0, r0, #(1 << 2)
-       str r0, [r1, #0x88]
-       add r1, r1, #4
-       subs r2, r2, #0x1
-       bne pad_loop
-.endm /* init_drive_strength */
-
-/* CPLD on CS4 setup */
-.macro init_cs4
-       ldr r0, =WEIM_BASE
-       ldr r1, =0x0000D843
-       str r1, [r0, #0x40]
-       ldr r1, =0x22252521
-       str r1, [r0, #0x44]
-       ldr r1, =0x22220A00
-       str r1, [r0, #0x48]
-.endm /* init_cs4 */
-
-.globl lowlevel_init
-lowlevel_init:
-
-       /* Redboot initializes very early AIPS, what for?
-        * Then it also initializes Multi-Layer AHB Crossbar Switch,
-        * M3IF */
-       /* Also setup the Peripheral Port Remap register inside the core */
-       ldr r0, =0x40000015        /* start from AIPS 2GB region */
-       mcr p15, 0, r0, c15, c2, 4
-
-       init_aips
-
-       init_max
-
-       init_m3if
-
-       init_drive_strength
-
-       init_cs4
-
-       /* Image Processing Unit: */
-       /* Too early to switch display on? */
-       REG     IPU_CONF, IPU_CONF_DI_EN        /* Switch on Display Interface 
*/
-       /* Clock Control Module: */
-       REG     CCM_CCMR, 0x074B0BF5            /* Use CKIH, MCU PLL off */
-
-       DELAY 0x40000
-
-       REG     CCM_CCMR, 0x074B0BF5 | CCMR_MPE                 /* MCU PLL on */
-       REG     CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS   /* Switch to 
MCU PLL */
-
-       /* PBC CPLD on CS4 */
-       mov     r1, #CS4_BASE
-       ldrh    r1, [r1, #0x2]
-       /* Is 27MHz switch set? */
-       ands    r1, r1, #0x10
-
-       /* 532-133-66.5 */
-       ldr     r0, =CCM_BASE
-       ldr     r1, =0xFF871D58
-       /* PDR0 */
-       str     r1, [r0, #0x4]
-       ldreq   r1, MPCTL_PARAM_532
-       ldrne   r1, MPCTL_PARAM_532_27
-       /* MPCTL */
-       str     r1, [r0, #0x10]
-
-       /* Set UPLL=240MHz, USB=60MHz */
-       ldr     r1, =0x49FCFE7F
-       /* PDR1 */
-       str     r1, [r0, #0x8]
-       ldreq   r1, UPCTL_PARAM_240
-       ldrne   r1, UPCTL_PARAM_240_27
-       /* UPCTL */
-       str     r1, [r0, #0x14]
-       /* default CLKO to 1/8 of the ARM core */
-       mov     r1, #0x000002C0
-       add     r1, r1, #0x00000006
-       /* COSR */
-       str     r1, [r0, #0x1c]
-
-       /* RedBoot sets 0x3f, 7, 7, 3, 5, 1, 3, 0 */
-/*     REG     CCM_PDR0, PDR0_CSI_PODF(0x3f) | PDR0_CSI_PRDF(7) | 
PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | 
PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/
-
-       /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */
-/*     REG     CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | 
PLL_MFN(0x23)*/
-       /* Default: 1, 4, 12, 1 */
-       REG     CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1)
-
-       /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */
-       REG     0xB8001010, 0x00000004
-       REG     0xB8001004, 0x006ac73a
-       REG     0xB8001000, 0x92100000
-       REG     0x80000f00, 0x12344321
-       REG     0xB8001000, 0xa2100000
-       REG     0x80000000, 0x12344321
-       REG     0x80000000, 0x12344321
-       REG     0xB8001000, 0xb2100000
-       REG8    0x80000033, 0xda
-       REG8    0x81000000, 0xff
-       REG     0xB8001000, 0x82226080
-       REG     0x80000000, 0xDEADBEEF
-       REG     0xB8001010, 0x0000000c
-
-       mov     pc, lr
-
-MPCTL_PARAM_532:
-       .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0))
-MPCTL_PARAM_532_27:
-       .word (((1-1) << 26) + ((15-1) << 16) + (9  << 10) + (13 << 0))
-UPCTL_PARAM_240:
-       .word (((2-1) << 26) + ((13-1) << 16) + (9  << 10) + (3  << 0))
-UPCTL_PARAM_240_27:
-       .word (((2-1) << 26) + ((9 -1) << 16) + (8  << 10) + (8  << 0))
diff --git a/board/freescale/mx31ads/mx31ads.c 
b/board/freescale/mx31ads/mx31ads.c
deleted file mode 100644
index ad89cb021db9..000000000000
--- a/board/freescale/mx31ads/mx31ads.c
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * Copyright (C) 2008, Guennadi Liakhovetski <l...@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#include <common.h>
-#include <netdev.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx-regs.h>
-#include <asm/arch/sys_proto.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int dram_init(void)
-{
-       /* dram_init must store complete ramsize in gd->ram_size */
-       gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
-                               PHYS_SDRAM_1_SIZE);
-       return 0;
-}
-
-int board_early_init_f(void)
-{
-       int i;
-
-       /* CS0: Nor Flash */
-       /*
-        * CS0L and CS0A values are from the RedBoot sources by Freescale
-        * and are also equal to those used by Sascha Hauer for the Phytec
-        * i.MX31 board. CS0U is just a slightly optimized hardware default:
-        * the only non-zero field "Wait State Control" is set to half the
-        * default value.
-        */
-       static const struct mxc_weimcs cs0 = {
-               /*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
-               CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  0, 15, 0,  0,  0),
-               /*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
-               CSCR_L(1,  0,   0,   0,  0,  1,  5,  0,  0,  0,   1,   1),
-               /*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
-               CSCR_A(0,   0,  7,  2,  0,  0,  2,  1,  0,  0,  0,  0,   0,   0)
-       };
-
-       mxc_setup_weimcs(0, &cs0);
-
-       /* setup pins for UART1 */
-       mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
-       mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
-       mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
-       mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
-
-       /* SPI2 */
-       mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
-       mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
-       mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
-       mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
-       mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
-       mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
-       mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
-
-       /* start SPI2 clock */
-       __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
-
-       /* PBC setup */
-       /* Enable UART transceivers also reset the Ethernet/external UART */
-       readw(CS4_BASE + 4);
-
-       writew(0x8023, CS4_BASE + 4);
-
-       /* RedBoot also has an empty loop with 100000 iterations here -
-        * clock doesn't run yet */
-       for (i = 0; i < 100000; i++)
-               ;
-
-       /* Clear the reset, toggle the LEDs */
-       writew(0xDF, CS4_BASE + 6);
-
-       /* clock still doesn't run */
-       for (i = 0; i < 100000; i++)
-               ;
-
-       /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
-       readb(CS4_BASE + 8);
-       readb(CS4_BASE + 7);
-       readb(CS4_BASE + 8);
-       readb(CS4_BASE + 7);
-
-       return 0;
-}
-
-int board_init(void)
-{
-       gd->bd->bi_boot_params = 0x80000100;    /* adress of boot parameters */
-
-       return 0;
-}
-
-int checkboard(void)
-{
-       printf("Board: MX31ADS\n");
-       return 0;
-}
-
-#ifdef CONFIG_CMD_NET
-int board_eth_init(bd_t *bis)
-{
-       int rc = 0;
-#ifdef CONFIG_CS8900
-       rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
-#endif
-       return rc;
-}
-#endif
diff --git a/board/freescale/mx31ads/u-boot.lds 
b/board/freescale/mx31ads/u-boot.lds
deleted file mode 100644
index 71a63f188e77..000000000000
--- a/board/freescale/mx31ads/u-boot.lds
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * January 2004 - Changed to support H4 device
- * Copyright (c) 2004 Texas Instruments
- *
- * (C) Copyright 2002
- * Gary Jennejohn, DENX Software Engineering, <ga...@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
-ENTRY(_start)
-SECTIONS
-{
-       . = 0x00000000;
-
-       . = ALIGN(4);
-       .text      :
-       {
-               *(.__image_copy_start)
-         /* WARNING - the following is hand-optimized to fit within    */
-         /* the sector layout of our flash chips!      XXX FIXME XXX   */
-
-         *                                     (.vectors)
-         arch/arm/cpu/arm1136/start.o          (.text*)
-         board/freescale/mx31ads/built-in.o    (.text*)
-         arch/arm/lib/built-in.o               (.text*)
-         net/built-in.o                        (.text*)
-         drivers/mtd/built-in.o                (.text*)
-
-         . = DEFINED(env_offset) ? env_offset : .;
-         env/embedded.o(.text*)
-
-         *(.text*)
-       }
-       . = ALIGN(4);
-       .rodata : { *(.rodata*) }
-
-       . = ALIGN(4);
-       .data : {
-               *(.data*)
-       }
-
-       . = ALIGN(4);
-
-       . = ALIGN(4);
-       .u_boot_list : {
-               KEEP(*(SORT(.u_boot_list*)));
-       }
-
-       . = ALIGN(4);
-
-       .image_copy_end :
-       {
-               *(.__image_copy_end)
-       }
-
-       .rel_dyn_start :
-       {
-               *(.__rel_dyn_start)
-       }
-
-       .rel.dyn : {
-               *(.rel*)
-       }
-
-       .rel_dyn_end :
-       {
-               *(.__rel_dyn_end)
-       }
-
-       .hash : { *(.hash*) }
-
-       .end :
-       {
-               *(.__end)
-       }
-
-       _image_binary_end = .;
-
-/*
- * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
- * __bss_base and __bss_limit are for linker only (overlay ordering)
- */
-
-       .bss_start __rel_dyn_start (OVERLAY) : {
-               KEEP(*(.__bss_start));
-               __bss_base = .;
-       }
-
-       .bss __bss_base (OVERLAY) : {
-               *(.bss*)
-                . = ALIGN(4);
-                __bss_limit = .;
-       }
-       .bss_end __bss_limit (OVERLAY) : {
-               KEEP(*(.__bss_end));
-       }
-
-       .dynsym _image_binary_end : { *(.dynsym) }
-       .dynbss : { *(.dynbss) }
-       .dynstr : { *(.dynstr*) }
-       .dynamic : { *(.dynamic*) }
-       .gnu.hash : { *(.gnu.hash) }
-       .plt : { *(.plt*) }
-       .interp : { *(.interp*) }
-       .gnu : { *(.gnu*) }
-       .ARM.exidx : { *(.ARM.exidx*) }
-}
diff --git a/configs/mx31ads_defconfig b/configs/mx31ads_defconfig
deleted file mode 100644
index 9a4622577c13..000000000000
--- a/configs/mx31ads_defconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-CONFIG_ARM=y
-CONFIG_TARGET_MX31ADS=y
-CONFIG_SYS_TEXT_BASE=0xA0000000
-# CONFIG_AUTO_COMPLETE is not set
-CONFIG_CMD_IMLS=y
-CONFIG_CMD_SPI=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_DHCP=y
-CONFIG_CMD_PING=y
-CONFIG_CMD_DATE=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_MXC_GPIO=y
-# CONFIG_MMC is not set
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_MXC_SPI=y
diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h
deleted file mode 100644
index 651b998a4a5a..000000000000
--- a/include/configs/mx31ads.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * Copyright (C) 2008, Guennadi Liakhovetski <l...@denx.de>
- *
- * Configuration settings for the MX31ADS Freescale board.
- *
- * SPDX-License-Identifier:    GPL-2.0+
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-#include <asm/arch/imx-regs.h>
-
- /* High Level Configuration Options */
-#define CONFIG_MX31            1               /* This is a mx31 */
-
-#define CONFIG_MACH_TYPE       MACH_TYPE_MX31ADS
-
-#define CONFIG_CMDLINE_TAG             1       /* enable passing of ATAGs */
-#define CONFIG_SETUP_MEMORY_TAGS       1
-#define CONFIG_INITRD_TAG              1
-
-/*
- * Size of malloc() pool
- */
-#define CONFIG_SYS_MALLOC_LEN          (CONFIG_ENV_SIZE + 128 * 1024)
-
-/*
- * Hardware drivers
- */
-
-#define CONFIG_MXC_UART
-#define CONFIG_MXC_UART_BASE   UART1_BASE
-
-#define CONFIG_HARD_SPI                1
-#define CONFIG_DEFAULT_SPI_BUS 1
-#define CONFIG_DEFAULT_SPI_MODE        (SPI_MODE_0 | SPI_CS_HIGH)
-
-/* PMIC Controller */
-#define CONFIG_POWER
-#define CONFIG_POWER_SPI
-#define CONFIG_POWER_FSL
-#define CONFIG_FSL_PMIC_BUS    1
-#define CONFIG_FSL_PMIC_CS     0
-#define CONFIG_FSL_PMIC_CLK    1000000
-#define CONFIG_FSL_PMIC_MODE   (SPI_MODE_0 | SPI_CS_HIGH)
-#define CONFIG_FSL_PMIC_BITLEN 32
-#define CONFIG_RTC_MC13XXX
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-#define CONFIG_LOADADDR                0x80800000      /* loadaddr env var */
-
-#define        CONFIG_EXTRA_ENV_SETTINGS                                       
\
-       "netdev=eth0\0"                                                 \
-       "uboot_addr=0xa0000000\0"                                       \
-       "uboot=mx31ads/u-boot.bin\0"                                    \
-       "kernel=mx31ads/uImage\0"                                       \
-       "nfsroot=/opt/eldk/arm\0"                                       \
-       "bootargs_base=setenv bootargs console=ttymxc0,115200\0"        \
-       "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "       \
-               "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"       \
-       "bootcmd=run bootcmd_net\0"                                     \
-       "bootcmd_net=run bootargs_base bootargs_nfs; "                  \
-               "tftpboot ${loadaddr} ${kernel}; bootm\0"               \
-       "prg_uboot=tftpboot ${loadaddr} ${uboot}; "                     \
-               "protect off ${uboot_addr} 0xa003ffff; "                \
-               "erase ${uboot_addr} 0xa003ffff; "                      \
-               "cp.b ${loadaddr} ${uboot_addr} ${filesize}; "          \
-               "setenv filesize; saveenv\0"
-
-#define CONFIG_CS8900
-#define CONFIG_CS8900_BASE     0xb4020300
-#define CONFIG_CS8900_BUS16            1       /* follow the Linux driver */
-
-/*
- * The MX31ADS board seems to have a hardware "peculiarity" confirmed under
- * U-Boot, RedBoot and Linux: the ethernet Rx signal is reaching the CS8900A
- * controller inverted. The controller is capable of detecting and correcting
- * this, but it needs 4 network packets for that. Which means, at startup, you
- * will not receive answers to the first 4 packest, unless there have been some
- * broadcasts on the network, or your board is on a hub. Reducing the ARP
- * timeout from default 5 seconds to 200ms we speed up the initial TFTP
- * transfer, should the user wish one, significantly.
- */
-#define CONFIG_ARP_TIMEOUT     200UL
-
-/*
- * Miscellaneous configurable options
- */
-
-#define CONFIG_SYS_MEMTEST_START       0               /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END         0x10000
-
-#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR
-
-/*-----------------------------------------------------------------------
- * Physical Memory Map
- */
-#define CONFIG_NR_DRAM_BANKS   1
-#define PHYS_SDRAM_1           CSD0_BASE
-#define PHYS_SDRAM_1_SIZE      (128 * 1024 * 1024)
-
-#define CONFIG_SYS_SDRAM_BASE          PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_RAM_ADDR       IRAM_BASE_ADDR
-#define CONFIG_SYS_INIT_RAM_SIZE       IRAM_SIZE
-#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - \
-                                               GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_ADDR        (CONFIG_SYS_INIT_RAM_ADDR + \
-                                               CONFIG_SYS_GBL_DATA_OFFSET)
-
-/*-----------------------------------------------------------------------
- * FLASH and environment organization
- */
-#define CONFIG_SYS_FLASH_BASE          CS0_BASE
-#define CONFIG_SYS_MAX_FLASH_BANKS     1               /* max number of memory 
banks */
-#define CONFIG_SYS_MAX_FLASH_SECT      262             /* max number of 
sectors on one chip */
-#define CONFIG_SYS_MONITOR_BASE        CONFIG_SYS_FLASH_BASE   /* Monitor at 
beginning of flash */
-#define CONFIG_SYS_MONITOR_LEN         (256 * 1024)    /* Reserve 256KiB */
-
-#define CONFIG_ENV_SECT_SIZE   (128 * 1024)
-#define CONFIG_ENV_SIZE                CONFIG_ENV_SECT_SIZE
-#define CONFIG_ENV_ADDR                (CONFIG_SYS_MONITOR_BASE + 
CONFIG_SYS_MONITOR_LEN)
-
-/* Address and size of Redundant Environment Sector    */
-#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
-#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
-
-/*-----------------------------------------------------------------------
- * CFI FLASH driver setup
- */
-#define CONFIG_SYS_FLASH_CFI                   1 /* Flash memory is CFI 
compliant */
-#define CONFIG_FLASH_CFI_DRIVER                1 /* Use drivers/cfi_flash.c */
-#define CONFIG_FLASH_SPANSION_S29WS_N  1 /* A non-standard buffered write 
algorithm */
-#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE      1 /* Use buffered writes (~10x 
faster) */
-#define CONFIG_SYS_FLASH_PROTECTION            1 /* Use hardware sector 
protection */
-
-/*
- * JFFS2 partitions
- */
-#define CONFIG_JFFS2_DEV       "nor0"
-
-#endif /* __CONFIG_H */
-- 
2.7.4

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