Skip the cache initialization, which can be done later on in U-Boot
proper, since this interferes with early DRAM initialization in TPL.

Signed-off-by: Marek Vasut <marek.vasut+rene...@gmail.com>
Cc: Nobuhiro Iwamatsu <iwama...@nigauri.org>
---
 arch/arm/mach-rmobile/lowlevel_init_ca15.S | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/mach-rmobile/lowlevel_init_ca15.S 
b/arch/arm/mach-rmobile/lowlevel_init_ca15.S
index a5dbbea9e1..ef2280bea4 100644
--- a/arch/arm/mach-rmobile/lowlevel_init_ca15.S
+++ b/arch/arm/mach-rmobile/lowlevel_init_ca15.S
@@ -11,6 +11,7 @@
 #include <linux/linkage.h>
 
 ENTRY(lowlevel_init)
+#ifndef CONFIG_TPL_BUILD
        mrc     p15, 0, r4, c0, c0, 5 /* mpidr */
        orr     r4, r4, r4, lsr #6
        and     r4, r4, #7 /* id 0-3 = ca15.0,1,2,3 */
@@ -83,6 +84,7 @@ _exit_init_l2_a15:
        bl s_init
 
        ldr     lr, [sp]
+#endif
        mov     pc, lr
        nop
 ENDPROC(lowlevel_init)
-- 
2.16.2

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