commit b4d956f6bc0f ("bootm: Align cache flush end address correctly")
aligns the end address of the cache flush operation to a cache-line size to
ensure lower-layers in the code accept the range provided and flush.

A similar action should be taken for the begin address of a cache flush
operation. The load address may not be aligned to a cache-line boundary, so
ensure the passed address is aligned.

Signed-off-by: Bryan O'Donoghue <>
Reported-by: Breno Matheus Lima <>
Cc: Simon Glass <>
 common/bootm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/common/bootm.c b/common/bootm.c
index adb1213..45d140c 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -447,7 +447,8 @@ static int bootm_load_os(bootm_headers_t *images, unsigned 
long *load_end,
                return err;
-       flush_cache(load, ALIGN(*load_end - load, ARCH_DMA_MINALIGN));
+       flush_cache(ALIGN(load, ARCH_DMA_MINALIGN),
+                   ALIGN(*load_end - load, ARCH_DMA_MINALIGN));
        debug("   kernel loaded at 0x%08lx, end = 0x%08lx\n", load, *load_end);

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