> Read-to-read/Write-to-write turnaround for same chip select > of DDR3 memory, BL/2+2 cycles is enough for these turnarounds. > Cutting down the turnaround from BL/2+4 to BL/2+2 will improve > the memory performance.
Please ignore this patch, I will provide one better solution to address this performance issue. Thanks, Dave _______________________________________________ U-Boot mailing list [email protected] http://lists.denx.de/mailman/listinfo/u-boot
