Add board level codes and configs for i.MX8QXP MEK board.
- Enabled DM driver:
FEC, LPUART, LPI2C, GPIO, SD/MMC, PCA953X, pinctrl, Power-domain
- Board defconfigs:
imx8qxp_mek_defconfig
Boot log:
"
U-Boot 2018.05-00384-g8907416f0e (May 28 2018 - 14:06:27 +0800)
CPU: Freescale i.MX8QXP revB A35 at 1200 MHz
Model: Freescale i.MX8QXP MEK
Board: iMX8QXP MEK
Boot: SD1
DRAM: 3 GiB
MMC: Actual rate for SDHC_0 is 333333333
Actual rate for SDHC_1 is 200000000
FSL_SDHC: 0, FSL_SDHC: 1
Loading Environment from MMC... OK
In: serial@5a060000
Out: serial@5a060000
Err: serial@5a060000
Net: No ethernet found.
Hit any key to stop autoboot: 0
"
Signed-off-by: Peng Fan <peng....@nxp.com>
---
arch/arm/mach-imx/imx8/Kconfig | 13 +++
board/freescale/imx8qxp_mek/Kconfig | 14 +++
board/freescale/imx8qxp_mek/MAINTAINERS | 6 ++
board/freescale/imx8qxp_mek/Makefile | 7 ++
board/freescale/imx8qxp_mek/imx8qxp_mek.c | 159 ++++++++++++++++++++++++++++++
configs/imx8qxp_mek_defconfig | 47 +++++++++
include/configs/imx8qxp_mek.h | 157 +++++++++++++++++++++++++++++
7 files changed, 403 insertions(+)
create mode 100644 board/freescale/imx8qxp_mek/Kconfig
create mode 100644 board/freescale/imx8qxp_mek/MAINTAINERS
create mode 100644 board/freescale/imx8qxp_mek/Makefile
create mode 100644 board/freescale/imx8qxp_mek/imx8qxp_mek.c
create mode 100644 configs/imx8qxp_mek_defconfig
create mode 100644 include/configs/imx8qxp_mek.h
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index 58cb19946f..d15dfe3a6e 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -10,4 +10,17 @@ config IMX8QXP
config SYS_SOC
default "imx8"
+choice
+ prompt "i.MX8 board select"
+ optional
+
+config TARGET_IMX8QXP_MEK
+ bool "Support i.MX8QXP MEK board"
+ select BOARD_LATE_INIT
+ select IMX8QXP
+
+endchoice
+
+source "board/freescale/imx8qxp_mek/Kconfig"
+
endif
diff --git a/board/freescale/imx8qxp_mek/Kconfig
b/board/freescale/imx8qxp_mek/Kconfig
new file mode 100644
index 0000000000..b67300d816
--- /dev/null
+++ b/board/freescale/imx8qxp_mek/Kconfig
@@ -0,0 +1,14 @@
+if TARGET_IMX8QXP_MEK
+
+config SYS_BOARD
+ default "imx8qxp_mek"
+
+config SYS_VENDOR
+ default "freescale"
+
+config SYS_CONFIG_NAME
+ default "imx8qxp_mek"
+
+source "board/freescale/common/Kconfig"
+
+endif
diff --git a/board/freescale/imx8qxp_mek/MAINTAINERS
b/board/freescale/imx8qxp_mek/MAINTAINERS
new file mode 100644
index 0000000000..e9bf0b35a3
--- /dev/null
+++ b/board/freescale/imx8qxp_mek/MAINTAINERS
@@ -0,0 +1,6 @@
+i.MX8QXP MEK BOARD
+M: Peng Fan <peng....@nxp.com>
+S: Maintained
+F: board/freescale/imx8qxp_mek/
+F: include/configs/imx8qxp_mek.h
+F: configs/imx8qxp_mek_defconfig
diff --git a/board/freescale/imx8qxp_mek/Makefile
b/board/freescale/imx8qxp_mek/Makefile
new file mode 100644
index 0000000000..f9ee8aeff3
--- /dev/null
+++ b/board/freescale/imx8qxp_mek/Makefile
@@ -0,0 +1,7 @@
+#
+# Copyright 2017 NXP
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += imx8qxp_mek.o
diff --git a/board/freescale/imx8qxp_mek/imx8qxp_mek.c
b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
new file mode 100644
index 0000000000..e74c3a2547
--- /dev/null
+++ b/board/freescale/imx8qxp_mek/imx8qxp_mek.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <linux/libfdt.h>
+#include <environment.h>
+#include <fsl_esdhc.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/imx8-pins.h>
+#include <asm/arch/iomux.h>
+#include <asm/arch/sys_proto.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
+ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+ (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
+ (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
+ (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
+ (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
+
+static iomux_cfg_t uart0_pads[] = {
+ SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
+ SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
+};
+
+static void setup_iomux_uart(void)
+{
+ imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
+}
+
+int board_early_init_f(void)
+{
+ sc_ipc_t ipchndl;
+ sc_err_t scierr;
+ /* Set UART0 clock root to 80 MHz */
+ sc_pm_clock_rate_t rate = 80000000;
+
+ ipchndl = gd->arch.ipc_channel_handle;
+
+ /* Power up UART0 */
+ scierr = sc_pm_set_resource_power_mode(ipchndl, SC_R_UART_0,
+ SC_PM_PW_MODE_ON);
+ if (scierr != SC_ERR_NONE)
+ return 0;
+
+ scierr = sc_pm_set_clock_rate(ipchndl, SC_R_UART_0, 2, &rate);
+ if (scierr != SC_ERR_NONE)
+ return 0;
+
+ /* Enable UART0 clock root */
+ scierr = sc_pm_clock_enable(ipchndl, SC_R_UART_0, 2, true, false);
+ if (scierr != SC_ERR_NONE)
+ return 0;
+
+ setup_iomux_uart();
+
+ return 0;
+}
+
+#ifdef CONFIG_MXC_GPIO
+#define IOEXP_RESET IMX_GPIO_NR(1, 1)
+
+static iomux_cfg_t board_gpios[] = {
+ SC_P_SPI2_SDO | MUX_MODE_ALT(4) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+ SC_P_ENET0_REFCLK_125M_25M | MUX_MODE_ALT(4) |
+ MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
+static void board_gpio_init(void)
+{
+ int ret;
+ struct gpio_desc desc;
+
+ ret = dm_gpio_lookup_name("gpio@1a_3", &desc);
+ if (ret)
+ return;
+
+ ret = dm_gpio_request(&desc, "bb_per_rst_b");
+ if (ret)
+ return;
+
+ dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+ dm_gpio_set_value(&desc, 0);
+ udelay(50);
+ dm_gpio_set_value(&desc, 1);
+
+ imx8_iomux_setup_multiple_pads(board_gpios, ARRAY_SIZE(board_gpios));
+
+ /* enable i2c port expander assert reset line */
+ gpio_request(IOEXP_RESET, "ioexp_rst");
+ gpio_direction_output(IOEXP_RESET, 1);
+}
+#endif
+
+int checkboard(void)
+{
+ puts("Board: iMX8QXP MEK\n");
+
+ print_bootinfo();
+
+ return 0;
+}
+
+int board_init(void)
+{
+#ifdef CONFIG_MXC_GPIO
+ board_gpio_init();
+#endif
+
+ return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+ puts("\nDDR ");
+}
+
+/*
+ * Board specific reset that is system reset.
+ */
+void reset_cpu(ulong addr)
+{
+ puts("SCI reboot request");
+ sc_pm_reboot(SC_IPC_CH, SC_PM_RESET_TYPE_COLD);
+ while (1)
+ putc('.');
+}
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ return 0;
+}
+#endif
+
+int board_mmc_get_env_dev(int devno)
+{
+ return devno;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+ env_set("board_name", "MEK");
+ env_set("board_rev", "iMX8QXP");
+#endif
+
+ return 0;
+}
diff --git a/configs/imx8qxp_mek_defconfig b/configs/imx8qxp_mek_defconfig
new file mode 100644
index 0000000000..15b63da839
--- /dev/null
+++ b/configs/imx8qxp_mek_defconfig
@@ -0,0 +1,47 @@
+CONFIG_ARM=y
+CONFIG_ARCH_IMX8=y
+CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-mek"
+CONFIG_TARGET_IMX8QXP_MEK=y
+CONFIG_SYS_TEXT_BASE=0x80020000
+CONFIG_CMD_IMPORTENV=n
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_DM=y
+CONFIG_CMD_CACHE=y
+
+CONFIG_DM_SERIAL=y
+CONFIG_FSL_LPUART=y
+CONFIG_OF_CONTROL=y
+CONFIG_DM_I2C=y
+# CONFIG_DM_I2C_COMPAT is not set
+CONFIG_SYS_I2C_IMX_LPI2C=y
+CONFIG_CMD_I2C=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+
+CONFIG_CMD_GPIO=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_BOOTDELAY=3
+CONFIG_IMX_BOOTAUX=y
+CONFIG_FS_FAT=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_MMC=y
+CONFIG_DM_MMC=y
+
+CONFIG_CMD_PING=y
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_DM_ETH=y
+# CONFIG_EFI_LOADER is not set
+
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
+
+CONFIG_PINCTRL=y
+CONFIG_PINCTRL_IMX8=y
+
+CONFIG_POWER_DOMAIN=y
+CONFIG_IMX8_POWER_DOMAIN=y
+
+CONFIG_ENV_IS_IN_MMC=y
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h
new file mode 100644
index 0000000000..f0aa1c7541
--- /dev/null
+++ b/include/configs/imx8qxp_mek.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef __IMX8QXP_MEK_H
+#define __IMX8QXP_MEK_H
+
+#include <linux/sizes.h>
+#include <asm/arch/imx-regs.h>
+
+#define CONFIG_REMAKE_ELF
+
+#define CONFIG_BOARD_EARLY_INIT_F
+
+/* Flat Device Tree Definitions */
+#define CONFIG_OF_BOARD_SETUP
+
+#undef CONFIG_CMD_EXPORTENV
+#undef CONFIG_CMD_IMPORTENV
+#undef CONFIG_CMD_IMLS
+
+#undef CONFIG_CMD_CRC32
+#undef CONFIG_BOOTM_NETBSD
+
+#define CONFIG_FSL_ESDHC
+#define CONFIG_FSL_USDHC
+#define CONFIG_SYS_FSL_ESDHC_ADDR 0
+#define USDHC1_BASE_ADDR 0x5B010000
+#define USDHC2_BASE_ADDR 0x5B020000
+#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
+
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
+
+/* GPIO configs */
+#define CONFIG_MXC_GPIO
+
+/* Initial environment variables */
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "script=boot.scr\0" \
+ "image=Image\0" \
+ "panel=NULL\0" \
+ "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0"
\
+ "fdt_addr=0x83000000\0" \
+ "fdt_high=0xffffffffffffffff\0" \
+ "boot_fdt=try\0" \
+ "fdt_file=fsl-imx8qxp-mek.dtb\0" \
+ "initrd_addr=0x83800000\0" \
+ "initrd_high=0xffffffffffffffff\0" \
+ "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
+ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
+ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
+ "mmcautodetect=yes\0" \
+ "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
+ "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr}
${script};\0" \
+ "bootscript=echo Running bootscript from mmc ...; " \
+ "source\0" \
+ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
+ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
+ "mmcboot=echo Booting from mmc ...; " \
+ "run mmcargs; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if run loadfdt; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "else " \
+ "echo wait for boot; " \
+ "fi;\0" \
+ "netargs=setenv bootargs console=${console} " \
+ "root=/dev/nfs " \
+ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
+ "netboot=echo Booting from net ...; " \
+ "run netargs; " \
+ "if test ${ip_dyn} = yes; then " \
+ "setenv get_cmd dhcp; " \
+ "else " \
+ "setenv get_cmd tftp; " \
+ "fi; " \
+ "${get_cmd} ${loadaddr} ${image}; " \
+ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
+ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
+ "booti ${loadaddr} - ${fdt_addr}; " \
+ "else " \
+ "echo WARN: Cannot load the DT; " \
+ "fi; " \
+ "else " \
+ "booti; " \
+ "fi;\0"
+
+#define CONFIG_BOOTCOMMAND \
+ "mmc dev ${mmcdev}; if mmc rescan; then " \
+ "if run loadbootscript; then " \
+ "run bootscript; " \
+ "else " \
+ "if run loadimage; then " \
+ "run mmcboot; " \
+ "else run netboot; " \
+ "fi; " \
+ "fi; " \
+ "else booti ${loadaddr} - ${fdt_addr}; fi"
+
+/* Link Definitions */
+#define CONFIG_LOADADDR 0x80280000
+
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
+
+/* Default environment is in SD */
+#define CONFIG_ENV_SIZE 0x1000
+#define CONFIG_ENV_OFFSET (64 * SZ_64K)
+#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
+
+#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
+
+/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */
+#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
+#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
+#define CONFIG_SYS_FSL_USDHC_NUM 2
+
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32 * 1024)) * 1024)
+
+#define CONFIG_SYS_SDRAM_BASE 0x80000000
+#define CONFIG_NR_DRAM_BANKS 3
+#define PHYS_SDRAM_1 0x80000000
+#define PHYS_SDRAM_2 0x880000000
+#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
+/* LPDDR4 board total DDR is 3GB */
+#define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */
+
+/* Serial */
+#define CONFIG_BAUDRATE 115200
+
+/* Monitor Command Prompt */
+#define CONFIG_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+#define CONFIG_SYS_CBSIZE 2048
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY 8000000 /* 8MHz */
+
+#ifndef CONFIG_DM_PCA953X
+#define CONFIG_PCA953X
+#define CONFIG_CMD_PCA953X
+#define CONFIG_CMD_PCA953X_INFO
+#endif
+
+#endif /* __IMX8QXP_MEK_H */
--
2.14.1
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