On Wed, May 30, 2018 at 09:02:18PM -0700, Vasily Khoruzhick wrote:
> That is necessary for using automatic calibration on A64 eMMC.
>
> Signed-off-by: Vasily khoruzhick <anars...@gmail.com>
> ---
> arch/arm/mach-sunxi/Kconfig | 1 +
> drivers/mmc/sunxi_mmc.c | 4 ++--
> 2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
> index 66fb094ac5..8a35033d1f 100644
> --- a/arch/arm/mach-sunxi/Kconfig
> +++ b/arch/arm/mach-sunxi/Kconfig
> @@ -257,6 +257,7 @@ config MACH_SUN50I
> select SUNXI_GEN_SUN6I
> select SUN6I_PRCM
> select SUNXI_HIGH_SRAM
> + select MMC_SUNXI_HAS_NEW_MODE
> select SUPPORT_SPL
> select SUNXI_DRAM_DW
> select SUNXI_DRAM_DW_32BIT
> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> index fe6d82c7b4..3bffb1b02e 100644
> --- a/drivers/mmc/sunxi_mmc.c
> +++ b/drivers/mmc/sunxi_mmc.c
> @@ -165,10 +165,10 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv,
> unsigned int hz)
> }
>
> if (new_mode) {
> -#ifdef CONFIG_MMC_SUNXI_HAS_NEW_MODE
> +#if defined(CONFIG_MMC_SUNXI_HAS_NEW_MODE) && !defined(CONFIG_MACH_SUN50I)
> val = CCM_MMC_CTRL_MODE_SEL_NEW;
> - setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
> #endif
> + setbits_le32(&priv->reg->ntsr, SUNXI_MMC_NTSR_MODE_SEL_NEW);
This is slightly more complicated than that, we have three cases we
need to support:
- Devices without the new mode (A31 and before)
- Devices with support for the new mode that can be toggled (A23/A33 to H3/H5
iirc)
- Devices with support for the new mode only
The latter was introduced by the A64, but is also found on other SoCs
now (such as the H6).
So I guess here we need an extra config option to handle it, or even
better, base the decision on the compatible like we're doing in Linux.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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