On 05/24/2018 09:58 PM, Marek Vasut wrote:
> The N25Q256(A) datasheet clearly states that this device does have
> a Flag Status Register and does update FSR PEC bit 7 during Program
> and Erase cycles to indicate the cycle is in progress. Enable the
> FSR PEC bit polling on this device to prevent data corruption.
>
> Signed-off-by: Marek Vasut <ma...@denx.de>
> Cc: Jagan Teki <ja...@openedev.com>
> Cc: Tom Rini <tr...@konsulko.com>
> ---
> drivers/mtd/spi/spi_flash_ids.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
> index 3b8f254ca2..fbc1bb6a5e 100644
> --- a/drivers/mtd/spi/spi_flash_ids.c
> +++ b/drivers/mtd/spi/spi_flash_ids.c
> @@ -130,8 +130,8 @@ const struct spi_flash_info spi_flash_ids[] = {
> {"n25q64a", INFO(0x20bb17, 0x0, 64 * 1024, 128, RD_FULL |
> WR_QPP | SECT_4K) },
> {"n25q128", INFO(0x20ba18, 0x0, 64 * 1024, 256, RD_FULL |
> WR_QPP) },
> {"n25q128a", INFO(0x20bb18, 0x0, 64 * 1024, 256, RD_FULL |
> WR_QPP) },
> - {"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL |
> WR_QPP | SECT_4K) },
> - {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL |
> WR_QPP | SECT_4K) },
> + {"n25q256", INFO(0x20ba19, 0x0, 64 * 1024, 512, RD_FULL |
> WR_QPP | E_FSR | SECT_4K) },
> + {"n25q256a", INFO(0x20bb19, 0x0, 64 * 1024, 512, RD_FULL |
> WR_QPP | E_FSR | SECT_4K) },
> {"n25q512", INFO(0x20ba20, 0x0, 64 * 1024, 1024, RD_FULL |
> WR_QPP | E_FSR | SECT_4K) },
> {"n25q512a", INFO(0x20bb20, 0x0, 64 * 1024, 1024, RD_FULL |
> WR_QPP | E_FSR | SECT_4K) },
> {"n25q1024", INFO(0x20ba21, 0x0, 64 * 1024, 2048, RD_FULL |
> WR_QPP | E_FSR | SECT_4K) },
>
So, where is this stuff, I don't see it in u-boot/master ?
--
Best regards,
Marek Vasut
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
https://lists.denx.de/listinfo/u-boot
