Hi Siva,

> -----Ursprüngliche Nachricht-----
> Von: Siva Durga Prasad Paladugu [mailto:siva...@xilinx.com]
> Gesendet: Montag, 11. Juni 2018 13:40
> An: ste...@herbrechtsmeier.net
> Cc: Herbrechtsmeier Dr.-Ing. , Stefan
> <stefan.herbrechtsme...@weidmueller.com>; u-boot@lists.denx.de;
> Michal Simek <michal.si...@xilinx.com>; mon...@monstr.eu
> Betreff: RE: [RFC PATCH] fpga: zynq: Add encrypted bitstream support with
> auto detect
> Interesting, I got your point. First of all,  Could you please let me know on
> how do you created the encrypted bitstream?

I use bootgen with the split option and the following bif file:

bootgen -image u-boot-spl-aes.bif -o i u-boot-spl-aes.bin -w on -encrypt efuse 
-split bin

        [bootloader, encryption=aes, authentication=rsa]u-boot-spl.elf

> I hope this is not the Xilinx bootgen flow(may be through other Xilinx flow)

To my knowledge you could only use bootgen because Xilinx doesn't documented 
the encryption even if I would like to integrate the encryption into mkimage.

> because, I don't think bootgen will update these fields while creating
> encrypted bitstream( need to re confirm on this) and my flow targets the
> Xilinx bootgen flow.

This fields are part of the encrypted binary bitstream and are needed for the 
fpga configuration via the pcap. They are documented inside the 

> Please let know your comments on this, based on which, will try to review
> and test your patch.

Let me know if you need more information or help.


Stefan Herbrechtsmeier
Software Developer Embedded Systems

Weidmüller - Your partner in Industrial Connectivity
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