On 05/29/2018 11:36 AM, Marek Vasut wrote: > Adjust the NAND register size on Arria10 to reflect reality. > > Signed-off-by: Marek Vasut <ma...@denx.de> > Cc: Chin Liang See <chin.liang....@intel.com> > Cc: Dinh Nguyen <dingu...@kernel.org> > --- > arch/arm/dts/socfpga_arria10.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm/dts/socfpga_arria10.dtsi > b/arch/arm/dts/socfpga_arria10.dtsi > index b51febda9c..2f935a21e9 100644 > --- a/arch/arm/dts/socfpga_arria10.dtsi > +++ b/arch/arm/dts/socfpga_arria10.dtsi > @@ -637,8 +637,8 @@ > #address-cells = <1>; > #size-cells = <1>; > compatible = "denali,denali-nand-dt", > "altr,socfpga-denali-nand"; > - reg = <0xffb90000 0x72000>, > - <0xffb80000 0x10000>; > + reg = <0xffb90000 0x20>, > + <0xffb80000 0x1000>; > reg-names = "nand_data", "denali_reg"; > interrupts = <0 99 4>; > dma-mask = <0xffffffff>; >
Acked-by: Dinh Nguyen <dingu...@kernel.org> _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
