Adjust the NAND register size on Arria10 to reflect reality.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Chin Liang See <[email protected]>
Cc: Dinh Nguyen <[email protected]>
---
arch/arm/dts/socfpga_arria10.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/socfpga_arria10.dtsi
b/arch/arm/dts/socfpga_arria10.dtsi
index b51febda9c..2f935a21e9 100644
--- a/arch/arm/dts/socfpga_arria10.dtsi
+++ b/arch/arm/dts/socfpga_arria10.dtsi
@@ -637,8 +637,8 @@
#address-cells = <1>;
#size-cells = <1>;
compatible = "denali,denali-nand-dt",
"altr,socfpga-denali-nand";
- reg = <0xffb90000 0x72000>,
- <0xffb80000 0x10000>;
+ reg = <0xffb90000 0x20>,
+ <0xffb80000 0x1000>;
reg-names = "nand_data", "denali_reg";
interrupts = <0 99 4>;
dma-mask = <0xffffffff>;
--
2.16.2
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