[U-Boot] [RFC 12/35] clk: sunxi: a64: Implement USB clocks

[Jagan Teki]

Implement USB clock enable and disble functions for
OHCI, EHCI, OTG and USBPHY gate and clock registers.

Signed-off-by: Jagan Teki <ja...@amarulasolutions.com>
---
 drivers/clk/sunxi/clk_a64.c | 62 ++++++++++++++++++++++++++++++++++---
 1 file changed, 58 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index fb9dec3173..3997432260 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -35,18 +35,72 @@ static ulong a64_clk_set_rate(struct clk *clk, ulong rate)
 
 static int a64_clk_enable(struct clk *clk)
 {
+       struct a64_clk_priv *priv = dev_get_priv(clk->dev);
+
        debug("%s(#%ld)\n", __func__, clk->id);
 
-       debug("  unhandled\n");
-       return -EINVAL;
+       switch (clk->id) {
+       case CLK_BUS_OTG:
+       case CLK_BUS_EHCI0:
+       case CLK_BUS_EHCI1:
+               setbits_le32(priv->base + 0x60,
+                            BIT(23 + (clk->id - CLK_BUS_OTG)));
+               return 0;
+       case CLK_BUS_OHCI0:
+       case CLK_BUS_OHCI1:
+               setbits_le32(priv->base + 0x60,
+                            BIT(28 + (clk->id - CLK_BUS_OHCI0)));
+               return 0;
+       case CLK_USB_PHY0:
+       case CLK_USB_PHY1:
+               setbits_le32(priv->base + 0xcc,
+                            BIT(8 + (clk->id - CLK_USB_PHY0)));
+               return 0;
+       case CLK_USB_OHCI0:
+               setbits_le32(priv->base + 0xcc, BIT(16));
+               return 0;
+       case CLK_USB_OHCI1:
+               setbits_le32(priv->base + 0xcc, BIT(17));
+               return 0;
+       default:
+               debug("  unhandled\n");
+               return -ENODEV;
+       }
 }
 
 static int a64_clk_disable(struct clk *clk)
 {
+       struct a64_clk_priv *priv = dev_get_priv(clk->dev);
+
        debug("%s(#%ld)\n", __func__, clk->id);
 
-       debug("  unhandled\n");
-       return -EINVAL;
+       switch (clk->id) {
+       case CLK_BUS_OTG:
+       case CLK_BUS_EHCI0:
+       case CLK_BUS_EHCI1:
+               clrbits_le32(priv->base + 0x60,
+                            BIT(23 + (clk->id - CLK_BUS_OTG)));
+               return 0;
+       case CLK_BUS_OHCI0:
+       case CLK_BUS_OHCI1:
+               clrbits_le32(priv->base + 0x60,
+                            BIT(28 + (clk->id - CLK_BUS_OHCI0)));
+               return 0;
+       case CLK_USB_PHY0:
+       case CLK_USB_PHY1:
+               clrbits_le32(priv->base + 0xcc,
+                            BIT(8 + (clk->id - CLK_USB_PHY0)));
+               return 0;
+       case CLK_USB_OHCI0:
+               clrbits_le32(priv->base + 0xcc, BIT(16));
+               return 0;
+       case CLK_USB_OHCI1:
+               clrbits_le32(priv->base + 0xcc, BIT(17));
+               return 0;
+       default:
+               debug("  unhandled\n");
+               return -ENODEV;
+       }
 }
 
 static struct clk_ops a64_clk_ops = {
-- 
2.17.1

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