On 08/01/2018 06:06 PM, Tom Rini wrote:
On Wed, Aug 01, 2018 at 11:52:36PM +0000, Tom Warren wrote:
I can add this to my PR list (but probably won't get one out until tomorrow
morning), or:
Acked-by: Tom Warren <[email protected]>
If that'll get it in sooner.
Applied, thanks!
Thanks. The Jetson TK1 tests all look good again.
Tom
-----Original Message-----
From: Tom Rini <[email protected]>
Sent: Wednesday, August 1, 2018 4:47 PM
To: Stephen Warren <[email protected]>
Cc: Tom Warren <[email protected]>; [email protected]; Simon Glass <[email protected]>;
Stephen Warren <[email protected]>; Mark Kettenis <[email protected]>; Alexander Graf
<[email protected]>
Subject: Re: [U-Boot] [PATCH] ARM: tegra: align carveout size
On Wed, Aug 01, 2018 at 05:26:10PM -0600, Stephen Warren wrote:
On 07/31/2018 12:38 PM, Stephen Warren wrote:
From: Stephen Warren <[email protected]>
Align the size of the carveout region to 2M. This ensures that the
size can be accurately represented by an LPAE page table that uses sections.
This solves a bug (hang at boot time soon after printing the DRAM
size) that only shows up when the following two commits are merged together:
d32e86bde8a3 ARM: HYP/non-sec: enable ARMV7_LPAE if HYP mode is
supported
6e584e633d10 ARM: tegra: avoid using secure carveout RAM
Cc: Mark Kettenis <[email protected]>
Cc: Alexander Graf <[email protected]>
Signed-off-by: Stephen Warren <[email protected]>
---
This should be applied quickly since it fixes a regression that
causes all boots to fail, which in turn causes test/py to reset and
"reflash" the target board for each test, which causes the test to take eons.
Could we apply this please? My Jenkins system will love you because of
it:-)
I'm looking for one more person to Ack this, thanks!
--
Tom
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