On 08/10/2018 02:56 PM, Simon Goldschmidt wrote:
> On 09.08.2018 23:57, Marek Vasut wrote:
>> On 08/09/2018 09:17 PM, Simon Goldschmidt wrote:
>>> [..]
>>> BTW, the DIP switches even allow the SoCrates to boot from fpga, which
>>> is what I'm currently working on. In this case, it seems like we need
>>> a separate config at least, but the dts can still be the same.
>> Presumably because the SPL needs different link address ?
> The linker address of course needs to be changed. Preventing the cpu
> accessing the FPGA OnChip RAM was a bit more tricky to debug, but it
> seems I have it working now.
> I guess we need a Kconfig option to enable the bridge reset changes and
> select the correct link address. I'll prepare a patch for that. Should I
> base it on top of my gen5 fixes series?

Arent you gonna repost that series anyway ? Just wrap it in I think.

> Additionally, to add the binary into an fpga, we need a hex file, maybe
> these can be automatically generated by mach-socfpga's Makefile when
> creating the SPL...

Don't we have a hex file target already ? Maybe you do want some
socrates_fpga custom defconfig for this setup.

Best regards,
Marek Vasut
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