On 10.09.2018 20:18, Dalon L Westergreen wrote:
On Mon, 2018-09-10 at 20:06 +0200, Simon Goldschmidt wrote:
On 10.09.2018 19:28, Dalon Westergreen wrote:
This patch set adds a possible hex output of the
u-boot-spl elf and enables said output for the
Intel Stratix10 device. Stratix10 requires a hex
output of the elf for creating the secure device manager
configuration bitstream.
I don't use Stratix10 but Cyclone5, but as I need a .hex to boot from
FPGA, I want to know how to solve this best.
So to understand this, again a question: is this the only way to boot
Stratix10? Or one of the possible boot methods?
Because reading "Intel® Stratix® 10 SoC FPGA Boot User Guide", it seems
like you would need the hex for "FPGA Configuration First Mode", but not
for "HPS Boot First Mode"?
Stratix 10 always requires this for boot. The configuration method in
s10 is very different. The
SDM, which is a security processor, copies the u-boot-spl data to the
S10 HPS onchip memory.
After this is done, the SDM releases the hps from reset. This is
regardless of the HPS boot media,
which could be SDMMC, etc, etc.
OK, reading the PDF I referenced in more detail, I think I can follow
you ;-)
If so, it would make Stratix10 and Cyclone5 more alike and a
configuration option (like "Boot from FPGA") could be used to control
CONFIG_OF_EMBED and enable creating the hex file for SPL.
I looked into how i could enable CONFIG_OF_EMBED only for the SPL
build and found no easy way. It was suggested to add something
like CONFIG_SPL_OF_EMBED but it still seemed this would require
touching a bunch of code. In the end, i really see no reason
in socfpga to have the devicetree separated from u-boot / spl.
We're planning multi-board support with one binary and multiple
devicetrees, but CONFIG_MULTI_DTB_FIT might also work for that...
The only thing that looks bad is that the U-Boot image file name changes...
I *am* working on fixing the "boot from FPGA" case for Cyclone5, so I'd
appreaciate it if we could share as much as possible between those
sub-architectures.
What difficulties are you having?
Time, mostly ;-)
But seriously speaking, Cyclone5 executes the SPL from FPGA onchip RAM
in this boot mode, and the bridges got disabled. That was the main
problem, I think. I've had patches sent, but they weren't clean enough
for 2018.09. I'll hope to find the time to work on them in the next
couple of weeks...
And I hope to find the time to test your patchsets on gen5, as well.
Simon
Simon
Dalon Westergreen (3):
common: add spl/u-boot-spl.hex target
arm: socfpga: stratix10: add CONFIG_SPL_TARGET
arm; socfpga: stratix10: Add CONFIG_OF_EMBED
Makefile | 5 +++++
configs/socfpga_stratix10_defconfig | 1 +
include/configs/socfpga_stratix10_socdk.h | 3 ++-
3 files changed, 8 insertions(+), 1 deletion(-)
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