Hi Simon, On Wed, 12 Sep 2018 at 17:25, Simon Shields <[email protected]> wrote: > > Hi, > > This patch series adds support for using U-Boot's SPL as the second > stage bootloader ("BL2") on Exynos4412 SoCs. > > - Patch #1 adds support for the EMMC/SD OM pin configuration, which is used > by the boards I tested on. > - Patch #2 configures the magic values used to indicate system suspend > state (which are identical to exynos5). > - Patch #3 renames the existing exynos4 clock/dmc initialisation code > to reflect the fact that it only supports exynos4210. > - Patches #4 and #5 add/fill in structs reflecting the PMU and TZASC > register layouts on exynos4412, respectively. > - Patch #6 adds the exynos4412 DMC and clock initialisation code and > enables building the SPL on exynos4412 platforms. > - Patch #7 enables building the "mkexynosspl" utility for exynos4 SoCs. > > The majority of the logic in patch #6 comes from a vendor u-boot dump > (2010.12!), however, small portions (mostly code used for 2GB RAM > initialisation) were reverse engineered from the vendor > bootloader found on a GT-N7100. > > This patch series has been tested on a GT-I9300 (exynos4412, 1GB RAM) > and a GT-N7100 (exynos4412 prime, 2GB RAM), with a few additional > patchsets applied for board/HW support (which I intend to upstream in > the future). > > Cheers, > Simon >
Could you elaborate more on how to generate stage bootloader (BL2) image, I am not aware of such process and what are next step to create SPL for Exynos platform. I have build these patches for Odroid-U3 boards, with no SPL enable. Best Regards -Anand _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
