On 11/29/2018 09:02 PM, Simon Goldschmidt wrote: > On 10.10.2018 14:56, Marek Vasut wrote: >> On 10/10/2018 02:55 PM, Simon Goldschmidt wrote: >>> This patch prevents disabling the FPGA bridges when >>> SPL or U-Boot is executed from FPGA onchip RAM. >>> >>> Signed-off-by: Simon Goldschmidt <[email protected]> >>> --- >>> >>> Changes in v5: >>> - changed inline function 'socfpga_is_fpga_slaves_addr(addr)' >>> to 'socfpga_is_booting_from_fpga()' >>> >>> Changes in v4: >>> - use an inline function in misc.h to check for the address >>> range instead of a macro in base_addr_ac5.h >>> >>> Changes in v3: >>> - use __image_copy_start to check if we are executing from FPGA >>> >>> Changes in v2: >>> - use less ifdefs and more C code for address checks >>> (but this gives a checkpatch warning because of comparing two >>> upper case constants) >>> - changed comments >>> >>> arch/arm/mach-socfpga/include/mach/base_addr_ac5.h | 1 + >>> arch/arm/mach-socfpga/include/mach/misc.h | 9 +++++++++ >>> arch/arm/mach-socfpga/misc_gen5.c | 9 ++++++++- >>> arch/arm/mach-socfpga/spl_gen5.c | 10 +++++++--- >>> 4 files changed, 25 insertions(+), 4 deletions(-) >>> >>> diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h >>> b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h >>> index bb9e3faa29..2725e9fcc3 100644 >>> --- a/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h >>> +++ b/arch/arm/mach-socfpga/include/mach/base_addr_ac5.h >>> @@ -6,6 +6,7 @@ >>> #ifndef _SOCFPGA_BASE_ADDRS_H_ >>> #define _SOCFPGA_BASE_ADDRS_H_ >>> +#define SOCFPGA_FPGA_SLAVES_ADDRESS 0xc0000000 >>> #define SOCFPGA_STM_ADDRESS 0xfc000000 >>> #define SOCFPGA_DAP_ADDRESS 0xff000000 >>> #define SOCFPGA_EMAC0_ADDRESS 0xff700000 >>> diff --git a/arch/arm/mach-socfpga/include/mach/misc.h >>> b/arch/arm/mach-socfpga/include/mach/misc.h >>> index 4fc9570a04..26609927c8 100644 >>> --- a/arch/arm/mach-socfpga/include/mach/misc.h >>> +++ b/arch/arm/mach-socfpga/include/mach/misc.h >>> @@ -6,6 +6,8 @@ >>> #ifndef _MISC_H_ >>> #define _MISC_H_ >>> +#include <asm/sections.h> >>> + >>> void dwmac_deassert_reset(const unsigned int of_reset_id, const u32 >>> phymode); >>> struct bsel { >>> @@ -23,6 +25,13 @@ static inline void socfpga_fpga_add(void) {} >>> #ifdef CONFIG_TARGET_SOCFPGA_GEN5 >>> void socfpga_sdram_remap_zero(void); >>> +static inline bool socfpga_is_booting_from_fpga(void) >>> +{ >>> + if ((__image_copy_start >= (char *)SOCFPGA_FPGA_SLAVES_ADDRESS) && >>> + (__image_copy_start < (char *)SOCFPGA_STM_ADDRESS)) >>> + return true; >>> + return false; >>> +} >>> #endif >>> #ifdef CONFIG_TARGET_SOCFPGA_ARRIA10 >>> diff --git a/arch/arm/mach-socfpga/misc_gen5.c >>> b/arch/arm/mach-socfpga/misc_gen5.c >>> index 429c3d6cd5..5fa40937c4 100644 >>> --- a/arch/arm/mach-socfpga/misc_gen5.c >>> +++ b/arch/arm/mach-socfpga/misc_gen5.c >>> @@ -177,6 +177,8 @@ static void socfpga_nic301_slave_ns(void) >>> void socfpga_sdram_remap_zero(void) >>> { >>> + u32 remap; >>> + >>> socfpga_nic301_slave_ns(); >>> /* >>> @@ -187,7 +189,12 @@ void socfpga_sdram_remap_zero(void) >>> setbits_le32(&scu_regs->sacr, 0xfff); >>> /* Configure the L2 controller to make SDRAM start at 0 */ >>> - writel(0x1, &nic301_regs->remap); /* remap.mpuzero */ >>> + remap = 0x1; /* remap.mpuzero */ >>> + /* Keep fpga bridge enabled when running from FPGA onchip RAM */ >>> + if (socfpga_is_booting_from_fpga()) >>> + remap |= 0x8; /* remap.hps2fpga */ >>> + writel(remap, &nic301_regs->remap); >>> + >>> writel(0x1, &pl310->pl310_addr_filter_start); >>> } >>> diff --git a/arch/arm/mach-socfpga/spl_gen5.c >>> b/arch/arm/mach-socfpga/spl_gen5.c >>> index be318cc0d9..ccdc661d05 100644 >>> --- a/arch/arm/mach-socfpga/spl_gen5.c >>> +++ b/arch/arm/mach-socfpga/spl_gen5.c >>> @@ -92,8 +92,11 @@ void board_init_f(ulong dummy) >>> /* Put everything into reset but L4WD0. */ >>> socfpga_per_reset_all(); >>> - /* Put FPGA bridges into reset too. */ >>> - socfpga_bridges_reset(1); >>> + >>> + if (!socfpga_is_booting_from_fpga()) { >>> + /* Put FPGA bridges into reset too. */ >>> + socfpga_bridges_reset(1); >>> + } >>> socfpga_per_reset(SOCFPGA_RESET(SDR), 0); >>> socfpga_per_reset(SOCFPGA_RESET(UART0), 0); >>> @@ -163,5 +166,6 @@ void board_init_f(ulong dummy) >>> hang(); >>> } >>> - socfpga_bridges_reset(1); >>> + if (!socfpga_is_booting_from_fpga()) >>> + socfpga_bridges_reset(1); >>> } >>> >> Applied, thanks ! > > Can this be merged to the main U-Boot repository soon? Or are you > waiting for something from me for this?
It was blocked by the stratix 10 patches, now I dropped them and I'm waiting for the CI to finish. > I'd like to sync our internal branch with this soon, to be able to > continue working on boot-from-FPGA (even if CONFIG_SPL_TEXT_BASE is > still not configurable for this). Try u-boot-socfpga/master for that . -- Best regards, Marek Vasut _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
