Hi Stefan, > From: Stefan Agner <[email protected]> > > The current value CTLUPD_AREF(0) is the reset value of the register, > so there is no need to write a value. If needed, the register can be > written using board specific CR settings. > > Signed-off-by: Stefan Agner <[email protected]> > Acked-by: Marcel Ziswiler <[email protected]> > --- > > arch/arm/mach-imx/ddrmc-vf610.c | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/arch/arm/mach-imx/ddrmc-vf610.c > b/arch/arm/mach-imx/ddrmc-vf610.c index d121a53898..d4926b5cee 100644 > --- a/arch/arm/mach-imx/ddrmc-vf610.c > +++ b/arch/arm/mach-imx/ddrmc-vf610.c > @@ -188,7 +188,6 @@ void ddrmc_ctrl_init_ddr3(struct > ddr3_jedec_timings const *timings, DDRMC_CR77_SWAP_EN, > &ddrmr->cr[77]); writel(DDRMC_CR78_Q_FULLNESS(timings->q_fullness) | > DDRMC_CR78_BUR_ON_FLY_BIT(12), &ddrmr->cr[78]); > - writel(DDRMC_CR79_CTLUPD_AREF(0), &ddrmr->cr[79]); > > writel(DDRMC_CR82_INT_MASK, &ddrmr->cr[82]); >
Reviewed-by: Lukasz Majewski <[email protected]> Best regards, Lukasz Majewski -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-59 Fax: (+49)-8142-66989-80 Email: [email protected]
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