On Mon, Dec 31, 2018 at 10:30 PM Jagan Teki <[email protected]> wrote: > > Although the previous version[1] is properly handled the clock gates > with enable and disable management, but this series is trying to add > some more complex Allwinner CLK architecture by handling parent clock > and other CLK attributes. > > Allwinner Clock control unit comprises of parent clocks, gates, multiplexers, > dividers, multipliers, pre/post dividers and flags etc. > > So, the U-Boot implementation of ccu has divided into gates and tree. > gates are generic clock configuration of enable/disable bit management > and these can be handled via ccu_clock_gate, which is almost same as > previous version changes. > > Tree clock has more Allwinner CLK attributes like clock type, fixed clocks, > misc clocks, mp, nk, nkm, nkmp, pre/post div, flags etc and these can be > managed via ccu_clock_tree. > > On top of initial clock gates supported from previous version, this > series is trying to add support for MP, NK, MISC, FIXED clock types > with get_rate functionality and that can eventually used by uart driver. > > On the summary, this would be an initial infrasture that can fit into > remaining clock handle support like set_rate, so the rest of code will > add on the requirement basics. > > Once this is fine, I will try to add code for other parts especially for > MMC since we have migration deadline for BLK, MMC, SCSI. > > So, please do let me know if anyone have any inputs. > > All these changes available at u-boot-sunxi/clk-next > > thanks, > Jagan. > > [1] https://patchwork.ozlabs.org/cover/962226/ > > Jagan Teki (26): > clk: Add Allwinner A64 CLK driver > reset: Add Allwinner RESET driver > clk: sunxi: Add Allwinner H3/H5 CLK driver > clk: sunxi: Add Allwinner A10/A20 CLK driver > clk: sunxi: Add Allwinner A10s/A13 CLK driver > clk: sunxi: Add Allwinner A31 CLK driver > clk: sunxi: Add Allwinner A23/A33 CLK driver > clk: sunxi: Add Allwinner A83T CLK driver > clk: sunxi: Add Allwinner R40 CLK driver > clk: sunxi: Add Allwinner V3S CLK driver > clk: sunxi: Implement UART clocks > clk: sunxi: Implement UART resets > clk: sunxi: Add Allwinner H6 CLK driver > sunxi: A64: Update sun50i-a64-ccu.h > clk: sunxi: Add ccu clock tree support > sunxi: Enable CLK > phy: sun4i-usb: Use CLK and RESET support > reset: Add reset valid > musb-new: sunxi: Use CLK and RESET support > sunxi: usb: Switch to Generic host controllers > usb: host: Drop [e-o]hci-sunxi drivers > clk: sunxi: Implement SPI clocks > spi: sun4i: Add CLK support > clk: sunxi: Implement A64 SPI clocks, resets > spi: Add Allwinner A31 SPI driver > board: sopine: Enable SPI/SPI-FLASH
I'm planning to pick gate clock patches and keep tree based clock for next version, let me know if anyone have any questions. _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
