[U-Boot] [PATCH] mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue

[Ye Li]

When sd/mmc work at DDR mode, like HS400/HS400ES/DDR52/DDR50 mode,
the output clock rate is half of the internal clock rate.

This patch set the DDR_EN bit first for DDR mode, hardware divide
the usdhc clock automatically, then follow the original sdr clock
setting method.

Signed-off-by: Haibo Chen <haibo.c...@nxp.com>
Signed-off-by: Ye Li <ye...@nxp.com>
---
 drivers/mmc/fsl_esdhc.c | 23 ++++++++++++++++++-----
 1 file changed, 18 insertions(+), 5 deletions(-)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 74007e2..87273c8 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -585,18 +585,31 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, 
struct mmc *mmc, uint clock)
 #else
        int pre_div = 2;
 #endif
-       int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
        int sdhc_clk = priv->sdhc_clk;
        uint clk;
 
+       /*
+        * For ddr mode, usdhc need to enable DDR mode first, after select
+        * this DDR mode, usdhc will automatically divide the usdhc clock
+        */
+       if (mmc->ddr_mode) {
+               writel(readl(&regs->mixctrl) | MIX_CTRL_DDREN, &regs->mixctrl);
+               sdhc_clk >>= 1;
+       }
+
        if (clock < mmc->cfg->f_min)
                clock = mmc->cfg->f_min;
 
-       while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
-               pre_div *= 2;
+       if (sdhc_clk / 16 > clock) {
+               for (; pre_div < 256; pre_div *= 2)
+                       if ((sdhc_clk / pre_div) <= (clock * 16))
+                               break;
+       } else
+               pre_div = 1;
 
-       while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
-               div++;
+       for (div = 1; div <= 16; div++)
+               if ((sdhc_clk / (div * pre_div)) <= clock)
+                       break;
 
        pre_div >>= 1;
        div -= 1;
-- 
2.7.4

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