On 01/17/2019 11:39 AM, Anup Patel wrote:
Add driver code for the SiFive FU540 PRCI IP block. This IP block
handles reset and clock control for the SiFive FU540 device and
implements SoC-level clock tree controls and dividers.
Based on code written by Wesley Terpstra <wes...@sifive.com>
found in commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
https://github.com/riscv/riscv-linux
Boot and PLL rate change were tested on a SiFive HiFive Unleashed
board.
Signed-off-by: Paul Walmsley <paul.walms...@sifive.com>
Signed-off-by: Atish Patra <atish.pa...@wdc.com>
Signed-off-by: Anup Patel <anup.pa...@wdc.com>
Can't say much about how the device works or whether this is in 100%
compliance to the U-Boot clk framework, but I didn't see anything
obviously wrong :).
Reviewed-by: Alexander Graf <ag...@suse.de>
Alex
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