On 2/1/19 5:04 AM, Chee, Tien Fong wrote:
> On Thu, 2019-01-31 at 15:55 +0100, Marek Vasut wrote:
>> On 1/31/19 3:51 PM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee <tien.fong.c...@intel.com>
>>>
>>> Add FPGA driver to support program FPGA with FPGA bitstream loading
>>> from
>>> filesystem. The driver are designed based on generic firmware
>>> loader
>>> framework. The driver can handle FPGA program operation from
>>> loading FPGA
>>> bitstream in flash to memory and then to program FPGA.
>>>
>>> Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com>
>>>
>>> ---
>>>
>>> changes for v7
>>> - Restructure the FPGA driver to support both peripheral bitstream
>>> and core
>>> bitstream bundled into FIT image.
>>> - Support loadable property for core bitstream. User can set
>>> loadable
>>> in DDR for better performance. This loading would be done in one
>>> large
>>> chunk instead of chunk by chunk loading with small memory buffer.
>>> ---
>>> arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts | 18 +
>>> .../include/mach/fpga_manager_arria10.h | 39 +-
>>> drivers/fpga/socfpga_arria10.c | 417
>>> ++++++++++++++++++++-
>>> 3 files changed, 457 insertions(+), 17 deletions(-)
>>>
>>> diff --git a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
>>> b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
>>> index 998d811..dc55618 100644
>>> --- a/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
>>> +++ b/arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts
>>> @@ -18,6 +18,24 @@
>>> /dts-v1/;
>>> #include "socfpga_arria10_socdk.dtsi"
>>>
>>> +/ {
>>> + chosen {
>>> + firmware-loader = &fs_loader0;
>> Shouldn't this be <&fs_loader0>; ?
>> How did this even pass the DTC ?
> So <> is compulsory required for phandle? No error complaint from DTC.
Yes
--
Best regards,
Marek Vasut
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