On 19. 02. 19 4:47, tien.fong.c...@intel.com wrote: > From: Tien Fong Chee <tien.fong.c...@intel.com> > > Add default fitImage file bundling FPGA bitstreams for Arria10. > > Signed-off-by: Tien Fong Chee <tien.fong.c...@intel.com> > > --- > > changes for v8 > - Reordered the images and fpga configurations. > - Removed the load property at core image. > > changes for v8
No reason to have separate v8 changes. > - Changed the FPGA node name to fpga-core and fpga-periph for both core and > periph bitstreams respectively. M -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Xilinx Microblaze Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP/Versal SoCs
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