On Wed, 27 Mar 2019 at 17:50, Trent Piepho <[email protected]> wrote: > > The cache flush of the kernel load area needs to be aligned outward to > the DMA cache alignment. The operations are simpler if we think of this > as aligning the start down, ALIGN_DOWN(load, ARCH_DMA_MINALIGN), and > aligning the end up, ALIGN(load_end, ARCH_DMA_MINALIGN), and then find > the length of the flushed region by subtracting the former from the > latter. > > Cc: Tom Rini <[email protected]> > Cc: Simon Glass <[email protected]> > Cc: Bryan O'Donoghue <[email protected]> > Signed-off-by: Trent Piepho <[email protected]> > --- > common/bootm.c | 7 +------ > 1 file changed, 1 insertion(+), 6 deletions(-)
Reviewed-by: Simon Glass <[email protected]> _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
