Hi Lukasz, On Mon, Apr 1, 2019 at 11:02 AM Lukasz Majewski <[email protected]> wrote: > > After the commit: "eth: dm: fec: Add gpio phy reset binding" > SHA1: efd0b791069af93e9d439a70d1fe2ae8994dbbfa > > The FEC ETH driver switched to PHY GPIO reset performed with data defined > in DTS. > For the HSC|DDC boards the GPIO reset signal is active low and hence the > wrong DTS description must be changed (otherwise the reset for ETH is not > properly setup).
We should probably use the same approach as in the kernel to avoid regressions with old dtbs. In the kernel the GPIO polarity passed in the 'phy-reset-gpios' property is ignored and it is assumed to be active low, unless 'phy-reset-active-high' is passed. Thanks _______________________________________________ U-Boot mailing list [email protected] https://lists.denx.de/listinfo/u-boot
